Yamaha RX-A710 - Page 82

Pin No. Port Name Function Name
ON
Detail of Function
I/O Logic
86 J10 GND
87 J11 GND
88 J12 GND
89 J13 GND
90 J14 VDDINT
91 J19 /AMS0 ---
92 J20 EXT_WAKE0 O Data Wake up indication 0
93 K1 PG9/TMR5/RSCLK0A/TACI5 NCPU_PIC_MISO O L act Buffer overflow flag of FPGA
94 K2 PG10/TMR6/TSCLK0A/TACI6 MT_DAC_Z O H act ZONE DAC mute
95 K7 VDDEXT
96 K8 VDDEXT
97 K9 GND
98 K10 GND
99 K11 GND
100 K12 GND
101 K13 GND
102 K14 VDDINT
103 K19 /AMS1 ---
104 K20 CLKOUT BF_CLK O Clock SDRAM clock
105 L1 PG7/TMR3/DR0PRIA/UART0TX DBG_MOSI O Data UART Tx for Debug
106 L2
PG8/TMR4/RFS0A/UART0RX/
TACI4
DBG_MISO I Data UART Rx for Debug
107 L7 VDDEXT
108 L8 VDDMEM
109 L9 GND
110 L10 GND
111 L11 GND
112 L12 GND
113 L13 GND
114 L14 VDDINT
115 L19 VPPOTP
116 L20 /AMS3 ---
117 M1 PG5/TMR1/PPI_FS2 --- O L act
118 M2 PG6/DT0PRIA/TMR2/PPI_FS3 APPLE_I2C_ON O H act APPLE I2C line switch control (H: connect, L: disconnect)
119 M7 VDDMEM
120 M8 VDDMEM
121 M9 GND
122 M10 GND
123 M11 GND
124 M12 GND
125 M13 GND
126 M14 VDDINT
127 M19 /AMS2 ---
128 M20 /ARE BF_N_ARE O L act EBIU read enable
129 N1 PG3/MISO/DR0SECA BF_SPI_MISO I Data
130 N2 PG4/MOSI/DT0SECA BF_SPI_MOSI O Data
131 N7 VDDMEM
132 N8 VDDMEM
133 N9 GND
134 N10 GND
135 N11 GND
136 N12 GND
137 N13 GND
138 N14 VDDINT
139 N19 /AWE BF_N_WR O L act EBIU write enable
140 N20 /AOE --- O L act
141 P1 PG1/SPISS/SPISEL1 SFLASH_N_CS O L act SPI flash memory chip select output (L: select)
142 P2 PG2/SCK BF_SPI_SCK O Clock SPI clock
143 P7 VDDMEM
144 P8 VDDMEM
145 P9 VDDMEM
146 P10 VDDMEM
147 P11 VDDMEM
148 P12 VDDINT
149 P13 VDDINT
150 P14 VDDINT
151 P19 ARDY --- I H act
152 P20 SCKE BF_SCKE O H act SDRAM CKE
82
RX-V671/HTR-6064/RX-A710
RX-V671/HTR-6064/
RX-A710
DRAFT