Agilent Technologies 54831A Service Guide

Chapter 8: Theory of Operation
Block-Level Theory
8–6
Figure 8-2
A
cquisition Block Diagram
Attenuator
Rattler
PreAmp & Dual
Tr
igger
Comparators
Front End
Upper
Lower
Attenuator
PreAmp & Dual
Trigger
Comparators
Front End
Upper
Lower
INTERFACE
CARD
PCI
Bridge
FPGA
Primary PCI Bus
Ribbon
Cable
Calibrat
or,
Probe
Comp
& Trig
Out
TrigOut
DACS
High Speed Trigger Circuitry
500
MHz
Comp.
Data
Delay
Circuit
Clock
Delay
Circuit
Logic Trigger
Scope Back Panel
AUX IN
AUX OUT
TTL OUT
Scope Front Panel
Probe Comp
CH 1 CH 2 CH 3 CH 4
CH 1
CH 2
CH 3
CH 4
ATrig
Hold Off
Data
Clock
Zeum
Data
Deceleration &
Processing
LSI Logic ASIC
Acquisition
Memory
8 8Mbit
SGRAMs
8 Bit
8 Bit
CLK
CLK
32 Bit
PHI4
32 Bit
PHI3
32 Bit
PHI2
32 Bit
PHI1
Addr
Data
Deceleration &
Processing
LSI Logic ASIC
Acquisition
Memory
8 8Mbit
SGRAMs
8 Bit
CLK
CLK
32 Bit
PHI4
32 Bit
PHI3
32 Bit
PHI2
32 Bit
PHI1
Addr
8 Bit
4GSa ADC
Trig 1
Trig 2
Fine Gate
Coarse Gate
Reference Clock
Generation
Interpolator
Sys
Trig
Secondary PCI Bus
CH 1 & 2
Digital 0-15
Acquistion Memory
ADC
Digital
0-15
AttenComparators Preamp
0-15 0-15
54830b10

Agilent Technologies 54831A Specifications

General

Brand	Agilent Technologies
Model	54831A
Category	Test Equipment
Language	English