54 Troubleshooting
Table 3-4. FET Troubleshooting Chart (continued)
Procedure Result
Static Troubleshooting
4. Measure the resistance across capacitor C201.
≈ 150 Ω.
5. Measure the resistance across the 15V bias input (E506 to E507).
≈ 1 kΩ in the forward
direction and 490 Ω in the
reverse direction.
Dynamic Troubleshooting
1. Turn off the power supply and remove the A3 FET Board with its heat sink assembly.
See "Disassembly
Procedures".
2. Short the collectors of Q251 and Q252 by connecting the collector (case) of each
transistor to common ( E507) .
3. Connect waveform generator to J200-1 and J200-2.
4. Set generator to produce a 20KHz, 20V p-p triangular waveform.
See Figure 3-14A.
5. Connect 15V from an external supply to E506 (positive) and E507 (common).
Note: All of the following measurements are taken with respect to E507 common, test
point
on A3 FET Board schematic diagram.
6. Check bias voltage at U203-1 .
+5V
7. While adjusting the external 15V supply input, check the bias trip point at U204-1 .
Voltage goes from low (0V)
to high (5V) at an input of
approximately 12V; and
from high to low at an input
of approximately 13V.
8. Set external supply input to + 15V and check drive 1 waveform at U201-10 and
drive 2 waveform at U201-12
.
See Figure 3-14B.
9. Check that pulses are present at U201-1 , U201-7 , U202-1 , and U202-7
.
See Figure 3-14C.
10. Pulses should be present on both sides of inductors L201-204 and L213-216 as follows:
Check the pulses on the driver transistor side (Q251-Q254) of each inductor.
Check the pulses on the FET regulator side (Q201-Q204, Q211, Q222, Q233, and
Q244) of each inductor.
If the waveforms do not have the fast step as shown in Figure 3-14, then the associated
FET gate input has an open circuit.
See Figure 3-14D.
See Figure 3-14E.
11. Measure the VREF voltage at U204-4 .
≈ 1.7V
12. Check the peak current limit by connecting a 68KΩ resistor from +5V (U201-9) to
U204-5.
All pulses turn off.
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