Akai VS-2EGN

MSLS10P
BUFFER DECORDER RAM
i
|
12} aconess 26 WoRDS x4 ar
ADDRESS
INPUT (16) 01
SENSE ouTPUT 02 | DATA
CIRCUIT BUFFER pos | OUTPUT
om
Gul aooress | 7 i
DECORDER |
:
|
CHIP. |
TNPUT OUERR. SELECTING H
1
1
1
1
ae 4
READ/ Dit Di2 Dis Dia cy Se 00
wane DATA CHIP SELECT OUTPUT CONTROL
INPUT
INPUT
INPUT
MB88301-P
13 BIT | DATA REGisTER | [ADDRESSLU
COINCIDENCE CIRCUIT
13 BIT COUNTER
ie
6BIT COUNTER (2) vac,
| (3) vaca
COINCIDENCE SIR. Ky COINCIDENCE CIR. Gace
| [eerrbararecisteR ] — [epi bata REGISTER | GBIT DATA REGISTER | @oacg
ft A a ae |
vss(6)
ft
j
Ove
(OS
ee
ee
ee
Oe
‘Schematic Diagram VS-2EGN.
166