Akai VS-2EGN

5. OPERATION CIRCUIT
5-1 OPERATION CIRCUIT COMPOSITION
MECHA-CON
CPU RST.
LF
S IN/OUT
S OUT/IN
MECHA-CON
CPU S.CLK
PWR OWN RSET PROT
FRONT PROCESSOR
MB88401
154K
1c7
VIDEO J
AFT
H SYNC
1¢3 AOM
LOi ICS E.Xtal
OAC HB8830!
HO.
LOI
CRT MNI227A
V SYNC
vow
INS
Fig. 7-76 shows the block diagram of the operation cir-
cuit. Peripheral circuits, such as EXT RAM (IC4: pro-
gram content holding), D/A converter (IC5: tuning volt-
age), CRT interface (C3), key matrix, power UP/DOWN
(IC1), Reset Pulse generator (IC2), channel/LED dis-
play circuit, and LPF, are arranged around the front
processor (IC7).
When the power is switched on, the 50/60 Hz signal en-
ters LF (Line Frequency), the power detector circuit
detects power UP, it is fed to IC2 1/2, and a RESET
pulse is generated there. This RESET pulse resets the
microcomputers of the front and SYS-CON, and data
<—IDL 5V
<—-GND
—< 1OL 33V
Twi
FILTER
CIB to 2
R61,62,63
are exchanged. using Sin/out, Sout/in, and S. CLK.
When the FUNCTION ON button is pressed, FUNC-
TION ON data is fed to the K-port of the front pro-
cessor from the key matrix. As a result, the mode
becomes the FUNCTION ON mode. Concurrently,
the output signal from the O-port is fed to each cir-
cuit for control.
@ Function-ON LED of the mode indication LED
lights.
® Channel display LED displays the last channel.
© D/A converter outputs data corresponding to that
channel, and supplies the tuning voltage to the
Service Manual VS-2EGN
Fig. 7-76 Block Diagram of Operation Circuit
tuner after it is converted to DC by the LPF.
A specified character pattern is written in to the
CRT interface (IC3) to correct the clock, and the
signal for TV superposition is output to VOW(Video
On Word), synchronized with H. SYNC and V.
SYNC. As a result, the clock correction charact-
er pattern is displayed in the top left part of the
TV screen.
As described above, it is so designed as to control peri-
pheral circuits by the front processor.
61