Akai VS-2EGN - Page 27

2-2-5 SECAM L PLAYBACK CIRCUIT
The PB signal fed from the pre-amplifier, is connected
to the LPF FL-12 (LCB-59), TR43, and TR45, which
select only the CHROMA signal components below 1.5
MHz. The luminance PB FM signal is attenuated. The
signal is now passed from the Video Board to the EGN
P.C
Board
via
Inter-Board
connection
PBC.
Then,
the
signal is directed to pass through the 1.07 MHz bell
filter composed of TR2, VL1, etc., whose characteris-
tic corrects for the 1.07 inverse bell filter used during
recording. Since the gain of the following stage limit-
er amplifier, is high compared with that during play-
back, the optimum limiter input level should be adjust-
ed.
The signal fed to ICI (uPC1004C EGN PCB) pin (1) is
subjected to a limiter operation. There the AM com-
ponent of the PB 1/4 fe CHROMA signal, which was
added during the process of electromagnetic conversion
is removed, and waveform shaping is performed in readi-
ness for the next stage double multiplying circuit. In
order to return to the original CHROMA signal, quad-
ruple multiplication is required. In IC1, double multi-
plication first of all is performed by the combination of
the quadrature detector and filter FL8.
1) IC1 (uPC1004C) function (EGN P.C Board)
The output is output from pin ®, directed to pass
through EF TR3, and then through the 2.2 MHz BPF
(FL2 and FL3) to attenuate noise, etc, other than funda-
mental signal after the frequency doubling operation.
Then, the signal is caused to pass through another fre-
quency doubling circuit composed of TR4, D1, and D2,
which restores the 1/4 count down signal to the original
condition during recording.
The next filter, FLA, is a 4.43 MHz BPF, which removes
noise, etc. other than the fundamental signal which has
been multiplied by 4. The CHROMA signal amplified
by TRS and noise gated (at Rec Mode) by TR6 is direct-
ed to pass through EF TR7, and further through the
4.29 MHz bell filter composed of VL2. The characteris-
tic corrected by the bell filter during the time of record-
ing process is returned to the original condition so as to
provide the BELL characteristic similar to the time it is
transmitted as a TV signal.
The final output is directed to pass through EF TR8. It
then passes to the Video Board via Inter-Board connec-
tion SL OUT on which the level is adjusted at C PB
LEVEL VRI5, fed to IC6 pin (5) via TR38, and mixed
with the PB-Y signal.
FLI
OL
VR2
LIMITER BALANCE
re AG © -y
| |
LIMITER QUADRATURE (8)
AMP OET
1 !
Le I
1Cl pPCIOO4c
| | | Limiter AMP output waveform (1/4 fc)
1
1 1
i
i
Depo
Wy et |
Loa tL
1
1 1
er] m ro
n : : i} { Output woveform passed through DOL of FLI
| ; |
|
|
| | |
Pin
output
waveform
(1/2
fc)
Fig. 7-17 Double Multiplying Circuit Block Diagram
This IC has a limiter amplifier and a frequency doubling
circuit. The frequency doubling circuit consists of a
quadrature detector and delay line (0.24 ys) FLI.
The signal passed through FL1 and the signal directly
Service Manual VS-2EGN
24
entering the quadrature detector, are detected which
results in a doubled frequency component at the out-
put.