Akai VS-2EGN - Page 68

5-4 CRT CONTROL (IC3: MN-1227A)
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FROM FRONT PROCESSOR
MN~ 12274
1) Operational outline
MN-1227A
has
a
built-in
character
pattern
generator.
Data
about
“the
display
position”
(60
points)
and
“characters
to
be
displayed”
(44
kinds)
are
read
at
the
leading
edge
and
the
trailing
edge
of
LDi
from
the
front
processor
into
O9—0g,
and
the
superposing
signal
is
out-
put
from
VOW,
synchronized
with
the
leading
edge
of
V
SYNC
and
H
SYNC.
R39,
R40,
and
C9
control
an
oscillator
at
about
6
MHz,
and
this
determines
the
character
size.
INS
is
controlled
by
the
front
processor
so
that
when
a
character
is
to
be
recorded,
it
becomes
‘H’,
and
it
is
fed
to
the
video
PCB.
VU,
VL
and
VH
are
tuner
band
switching
signals.
When
any
one
becomes
‘H’,
that
band
alone
is
selected.
2) Data loading
Data
are
loaded
into
the
MN1227A
data
memory
in
any
of
the
following
two
modes.
(@) Direct address mode (ADM=‘L’)
When
ADM
is
at
‘L’
level
(Refer
to
Fig.
7-84),
DAg—
DAg
7-bit
data
is
latched
at
the
memory
address
register
at
the
time
when
the
signal
fed
to
LDi
terminal
changes
from
‘L’
to
‘H’,
and
DAo—DAs
6-bit
data
is
loaded
into
the
memory
address
appointed
by
the
memory
address
register
at
the
time
when
the
signal
at
the
LDi
terminal
changes
from
‘H’
to
‘L’.
® Address increment mode (ADM=‘H’)
In
the
case
when
ADM
is
at
the
‘H’
level
(refer
to
Fig.
7-
85),
the
data
already
latched
at
the
memory
address
re-
gister
is
incremented
when
the
signal
fed
to
LDi
termi-
nal
changes
from
‘L’
to
‘H’,
and
DAg—DAsg
6-bit
data
is
loaded
the
memory
address
specified
by
the
memory
ad-
dress
register
after
the
increment
mode
is
complete,
as
the
signal
at
the
LDi
terminal
changes
from
‘H’
to
‘L’.
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V. Sync
FROM VIDEO
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Fig. 7-83 CRT Interface
ADM
“LY
LEVEL
DAO to DAG
ADDRESS(7 bits, DETA(6 bits)
Fig.
7-84
In
the
case
of
ADM=‘L’
DM
my
ee
LDi / \
DAO to DAG
ADDRESS(7
bits
DATA(6
bits)
Fig.
7-85
In
the
case
of
ADM=
—_—
$$
Service
Manual
VS-2EGN
———_——___
65