AMD XILINX VPK180 - Page 29

PMC and LPD MIO
The following secons provide the MIO peripheral mapping implemented on the VPK180
evaluaon board. See the Versal ACAP Technical Reference Manual (AM011) for more informaon
on MIO peripheral mapping. Addional signal connecvity can be located in the following
schemac secons:
• Bank 500: See schemac page 20
• Bank 501: See schemac page 21
• Bank 502: See schemac page 21
The following table provides MIO peripheral mapping implemented on the VPK180 evaluaon
board. The ACAP bank 500, 501, and 502 mappings are listed in the following table.
Chapter 3: Board Component Descriptions
UG1582 (v1.0) February 21, 2023 www.xilinx.com
VPK180 Board User Guide 29
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