Versal ACAP Configuration
The Versal XCVP1802 ACAP boot process is described in the “Plaorm Boot, Control, and
Status” secon of the Versal ACAP Technical Reference Manual (AM011). The VPK180 board
supports a subset of the modes documented in the technical reference manual via onboard boot
opons. The mode DIP switch SW1 conguraon opon sengs are listed in the following table.
Table 5: Mode Switch SW1 Configuration Option Settings
Boot Mode Mode Pins [0:3]
2
Mode SW1 [1:4]
2
JTAG
0000
1,3
ON, ON, ON, ON
QSPI32
0100
ON, OFF, ON, ON
SD1 (SD 3.0)
0111
ON, OFF, OFF, OFF
Notes:
1. Default switch setting.
2. Mode DIP SW1 poles [1:4] correspond to U1 XCVP1802 MODE[0:3].
3. Mode DIP SW1 individual switches ON=LOW (p/d to GND)=0, OFF=HIGH (p/u to VCCO)=1.
JTAG
The Vivado
®
, Xilinx SDK, or third-party tools can establish a JTAG connecon to the Versal
ACAP in the two ways described in this secon.
• FTDI FT4232 USB-to-JTAG/USB-UART device (U20) connected to USB 2.0 type-C connector
(J369), which requires:
○ Set boot mode SW1 for JTAG as indicated in the "Mode Switch SW1 Conguraon Opon
Sengs" table in Versal ACAP Conguraon.
○ On the 3-pin JTAG MUX, enable header J37 to enable the JTAG MUX. Move the 2-pin
jumper to be installed on pins 2-3. See Default Jumper and Switch Sengs for defaults and
Board Component Locaon for locaon.
○ Set 2-pole DIP SW3[1:2] set to 10 (OFF, ON) for JTAG MUX channel 2 FT4232 U20
bridge.
○ Power-cycle the VPK180 evaluaon board or press the power-on reset (POR) pushbuon
(SW2). SW2 is near the USB-C JTAG port J369 in the gure in Board Component Locaon).
• JTAG pod at cable connector J36 (2 mm 2x7 shrouded/keyed), which requires:
Note: In this mode, the FT4232 device (U20) UART funconality connues to be available.
○ Set boot mode SW1 for JTAG as indicated in the "Mode Switch SW1 Conguraon Opon
Sengs" table in Versal ACAP Conguraon.
Chapter 2: Board Setup and Configuration
UG1582 (v1.0) February 21, 2023 www.xilinx.com
VPK180 Board User Guide 21