AMD XILINX VPK180 - Appendix B: Xilinx Design Constraints; Overview

Appendix B
Xilinx Design Constraints
Overview
The Xilinx
®
design constraints (XDC) le template for the VPK180 board provides for designs
targeng the VPK180 evaluaon board. Net names in the constraints listed correlate with net
names on the latest VPK180 evaluaon board schemac. Idenfy the appropriate pins and
replace the net names with net names in the user RTL.
See the Vivado Design Suite User Guide: Using Constraints (UG903) for more informaon.
The HSPC FMCP connectors J51 is connected to ACAP U1 banks powered by the variable
voltage VADJ_FMC. Because dierent FMC cards implement dierent circuitry, the FMC bank
I/O standards must be uniquely dened by each customer. See LPD MIO[23]: VADJ_FMC Power
Rail for more details on the VADJ_FMC power rail.
IMPORTANT!
See the VPK180 board documentaon ("Board Files" check box) for the XDC le.
Appendix B: Xilinx Design Constraints
UG1582 (v1.0) February 21, 2023 www.xilinx.com
VPK180 Board User Guide 72
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