AMD XILINX VPK180 - Page 45

Table 15: PMC MIO[49] and LPD MIO[13,15:16,20] Power Domains
ACAP Pin Signal Power Domains
PMC MIO49 VCC_PSLP_EN LPDMGTYAVCC, VCCO_502, VCC_PSLP_CPM5,
LPDMGTYAVTT
LPD MIO 13 VCC_SOC_EN VCC_SOC
LPD MIO 15 VCC_PSFP_EN VCC_PSFP
LPD MIO 16 VCC1V1_LP4_AUX_EN VCCAUX,VCC1V1_LP4
LPD MIO 20 VCC_PL_EN VCCINT
LPD MIO 23 VADJ_FMC_EN VADJ_FMC
Note: See LPD MIO[23]: VADJ_FMC Power Rail for more informaon.
LPD MIO[21:22] Fan PWM
The ACAP PS bank 502 MIO21 (MIO21_FAN_PWM_VERSAL) is connected to J347 pin 3. When
J347 is selected as 2-3 (see Jumpers for defaults), the ACAP is able to control the fan PWM
speed. A controller applicaon must be created to drive this logic. The ACAP PS bank 502
MIO22 (MIO22_FAN_TACH_VERSAL) is connected J348 pin 3. This signal is fed by a 2N7002
MOSFET (Q46), which is in turn connected to the 12V fan tachometer feedback. The 2N7002 is
a N-Channel 60 V MOSFET. For more details, see Cooling Fan Connector.
LPD MIO[23]: VADJ_FMC Power Rail
The VPK180 evaluaon board implements the ANSI/VITA 57.4 IPMI support funconality. The
power control of the VADJ_FMC power rail is managed by the ZU4 U125 system controller. This
rail powers FMCP HSPC J51 VADJ pins, as well as the XCVP1802 U1 VCCO on the FMCP
interface banks 709 and 710. The valid values of the VADJ_FMC rail are 0, 1.2V, or 1.5V. At
power on, the system controller detects if an FMC module is installed on J51. The Versal ACAP
also has control over the acve-High enable line on the voltage regulator.
If the Versal ACAP has enabled the voltage regulator (acve-High), the following sequence of
acons occur:
• If no card is aached to a FMCP connector, the VADJ_FMC voltage is set to 1.5V
• When an FMC card is aached, its IIC EEPROM is read to nd a VADJ voltage supported by
both the VPK180 board and the FMC module, within the available choices of 0, 1.0V, 1.2V, or
1.5V
• If no valid informaon is found, or no voltage range can be matched in an aached FMC card
IIC EEPROM, the VADJ_FMC rail is set to 0.0V
The system controller user interface allows the FMC IPMI roune to be overridden and an
explicit value can be set for the VADJ_FMC rail. The override mode is useful for FMC mezzanine
cards that do not contain valid IPMI EPROM data dened by the ANSI/VITA 57.4 specicaon.
Chapter 3: Board Component Descriptions
UG1582 (v1.0) February 21, 2023 www.xilinx.com
VPK180 Board User Guide 45
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