AMD XILINX VPK180 - Page 56

Table 17: Transceiver Mapping (cont'd)
VPK180 XCVP1802 LSVC4072 GTY/GTM Mapping
PCIe
X1Y0
GTYP
Quad 200
X1Y0 CA
[LS]
ch3 FMC DP3
ch2 FMC DP2
ch1 FMC DP1
ch0 FMC DP0
refclk1 [UNUSED]
refclk0 FMCP1_GBTCLK0
GTYP Transceivers
[Figure 3, callout 1]
The ACAP (U1) bank 200 and bank 201 GTYP transceivers are wired to the FMCP connector
(J51). See schemac pages 9 and 46 for details.
The GTY/GTYP transceivers in the Versal architecture are power-ecient transceivers,
supporng line rates from 1.25 Gb/s to 32.75 Gb/s. The GTY/GTYP transceivers are highly
congurable and ghtly integrated with the programmable logic resources of the Versal
architecture. For more informaon, see the Versal ACAP GTY and GTYP Transceivers Architecture
Manual (AM002).
GTYP102/104: High-speed Debug Port Connectivity
[Figure 3, callout 9]
See the Versal Architecture and Product Data Sheet: Overview (DS950) for more informaon about
the high-speed debug port (HSDP) feature.
See schemac pages 8 and 36, as well as the VPK180 Evaluaon Board website for more details
on connecvity. See schemac page 8 for details on the clocking conguraon.
GTYP200/201: FPGA Mezzanine Card Interface
[Figure 3, callout 17]
The detailed ACAP connecons for the feature described in this secon are documented in the
VPK180 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
FMC+ Connector Type
The Samtec SEAF series 1.27 mm (0.050 in) pitch mates with the SEAM series connector. For
more informaon about the SEAF series connectors, see the Samtec, Inc. website. The 560-pin
FMC+ connector dened by the FMC specicaon (see Appendix A: VITA 57.4 FMCP Connector
Pinouts) provides connecvity for up to:
Chapter 3: Board Component Descriptions
UG1582 (v1.0) February 21, 2023 www.xilinx.com
VPK180 Board User Guide 56
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