AMD XILINX VPK180 - Page 57

• 160 single-ended or 80 dierenal user-dened signals
• 24 transceiver dierenal pairs
• 6 transceiver (GBTCLK) dierenal clocks
• 4 dierenal (CLK) clocks
• 1 dierenal (REFCLK) clock (both C2M and M2C pairs)
• 1 dierenal (SYNC) clock (both C2M and M2C pairs)
• 239 ground and 17 power connecons
For more informaon about the VITA 57.4 FMC+ specicaon, see the VITA FMC Markeng
Alliance website.
GTM Transceivers
[Figure 3, callout 1]
The GTM transceiver in the Versal Premium Series is a high-performance transceiver, supporng
a maximum line rate 112.0 Gb/s PAM4. The GTM transceiver is a ghtly integrated
programmable logic resource of the ACAP and the integrated networking IP, such as the DCMAC
or MRMAC.
For each of the interfaces described in the following secons, see the table in the Transceivers
secon. This table depicts the mapping from quads, channels, to lanes, along with associated
hardened IP and associated clocks.
GTM109/110/115/116: SFPDD1/2/3/4
[Figure 3, callout 15]
• The ACAP (U1) bank 109 GTM transceivers are wired to the SFPDD1 connector J350.
• The ACAP (U1) bank 110 GTM transceivers are wired to the SFPDD2 connector J352.
• The ACAP (U1) bank 115 GTM transceivers are wired to the SFPDD3 connector J385.
• The ACAP (U1) bank 116 GTM transceivers are wired to the SFPDD4 connector J351.
The connector is a Molex connector 2047301000, rated at 56 Gb/s per lane. The evaluaon
board has been opmized for 56 Gb/s per lane to provide 100GAUI-1 funconality.
For connecvity details, see the table in the Transceivers secon and schemac pages 63/64.
See the Versal ACAP GTM Transceivers Architecture Manual (AM017) for more details on 112 Gb/s
GTM-Quad conguraons.
GTM208/209/210/211: QSFPDD1/2
[Figure 3, upper callout 14]
Chapter 3: Board Component Descriptions
UG1582 (v1.0) February 21, 2023 www.xilinx.com
VPK180 Board User Guide 57
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