AMD Xilinx ZCU670 - Zynq Ultrascale+ Rfsoc XCZU67 DR

Zynq UltraScale+ RFSoC XCZU67DR
Zynq UltraScale+ RFSoC ZU67DR uses a mul-stage boot process documented in the Boot and
Conguraon chapter of the Zynq UltraScale+ Device Technical Reference Manual (UG1085).
Switch SW2 conguraon opon sengs are idened in the following table.
Table 5: Mode Switch SW2 Configuration Option Settings
Mode Mode Pins [3:0] Mode SW2 [4:1]
2
JTAG
0000
ON,ON,ON,ON
QSPI32
0010
1
ON,ON,OFF,ON
SD
1110
OFF,OFF,OFF,ON
Notes:
1. Default switch setting.
2. Switch OFF = 1 = High; ON = 0 = Low. See callout 11 in Table 4.
JTAG
Vivado
®
Design Suite or third-party tools can establish a JTAG connecon to the Zynq UltraScale
+ RFSoC through the FTDI FT4232 USB-to-JTAG/USB UART device (U29) connected to micro-
USB connector (J24).
QSPI
Use the following steps to boot from the dual QSPI non-volale conguraon memory.
1. Store a valid Zynq UltraScale+ RFSoC boot image into the QSPI ash devices (U11, U12,
MIO[0:12] QSPI interface).
2. Set the boot mode pins SW2 [4:1] as indicated in the table above for QSPI32.
3. Either power-cycle or press the power-on reset (POR) pushbuon. SW2 is callout 11 in
Figure 3.
SD
Use the following steps to boot from an SD card.
1. Store a valid Zynq UltraScale+ RFSoC boot image le onto an SD card (plugged into SD
socket J23) connected to the MIO[39:51] SD interface.
2. Set the boot mode pins SW3 [4:1] as indicated in the table above for SD.
3. Either power-cycle or press the power-on reset (POR) pushbuon. SW2 is callout 11 in
Figure 3.
Chapter 2: Board Setup and Configuration
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 18
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