AMD Xilinx ZCU670 - Appendix B: Xilinx Design Constraints; Overview

Appendix B
Xilinx Design Constraints
Overview
The Xilinx design constraints (XDC) le template for the ZCU670 board provides for designs
targeng the ZCU670 evaluaon board. Net names in the constraints listed correlate with net
names on the latest ZCU670 evaluaon board schemac. Idenfy the appropriate pins and
replace the net names with net names in the user RTL. See the Vivado Design Suite User Guide:
Using Constraints (UG903) for more informaon.
The HSPC FMCP connector J28 is connected to Zynq
®
UltraScale+™ RFSoC U1 banks powered
by the variable voltage VADJ_FMC. The FMC bank I/O standards must be uniquely dened by
each customer because dierent FMC cards implement dierent circuitry.
IMPORTANT!
To access the XDC le, click the Documentaon tab on the ZCU670 Evaluaon Board
website and select Board Files under Document Type.
Appendix B: Xilinx Design Constraints
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 64
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