AMD Xilinx ZCU670 - Page 26

The 4 GB, 32-bit wide DDR4 memory system is comprised of four 1 Gb x 8 SDRAM (Micron
MT40A1G8SA-075), U96-U99. This memory system is connected to PL-side ZU67DR banks 64
and 65. The DDR4 0.6V PL_DDR4_C0_VTT terminaon voltage is supplied from
TPS51200DRCT sink-source regulator U79.
• Manufacturer: Micron
• Part Number: MT40A1G8SA-075
• Descripon:
○
8 Gb (1 Gb x 8)
○ 1.2V 78-ball FBGA
○ DDR4-2666
The ZCU670 ZU67DR RFSoC PL DDR interface performance is documented in the Zynq
UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteriscs (DS926).
The ZCU670 board DDR4 32-bit component memory interface adheres to the constraints
guidelines documented in the PCB guidelines for DDR4 secon of UltraScale Architecture PCB
Design User Guide (UG583). The ZCU670 DDR4 component interface is a 40Ω impedance
implementaon. Other memory interface details are also available in the UltraScale Architecture-
Based FPGAs Memory IP LogiCORE IP Product Guide (PG150).
For addional details, see the Micron MT40A1G8SA-075 data sheet on the Micron Technology
website.
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU670 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
PSMIO
The following table provides PS MIO peripheral mapping implemented on the ZCU670 board.
See the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for more informaon on PS
MIO peripheral mapping.
Table 7: MIO Peripheral Mapping
MIO[0:25] Bank 500 MIO[26:51] Bank 501 MIO[52:77] Bank 502
0 QSPI_LWR 26 PMU IN 52 USB0
1 QSPI_LWR 27 MIO27 SFP3_TX_DISABLE_B 53 USB0
2 QSPI_LWR 28 MIO28 SFP2_TX_DISABLE_B 54 USB0
3 QSPI_LWR 29 MIO29 SFP1_TX_DISABLE_B 55 USB0
4 QSPI_LWR 30 MIO30 SFP0_TX_DISABLE_B 56 USB0
5 QSPI_LWR 31 Not assigned/no connect 57 USB0
6 Not assigned/no connect 32 PMU GPO 58 USB0
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 26
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