AMD Xilinx ZCU670 - Page 28

• Data rate: Various depending on Single/Dual/Quad mode
The conguraon and Quad-SPI secon of the Zynq UltraScale+ Device Technical Reference Manual
(UG1085) provides details on using the Quad-SPI ash memory. For more QSPI details, see the
Micron MT25QU02GCBB8E12-0SIT data sheet on the Micron Technology website.
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU670 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
GPIO (MIO 13, 38)
These two GPIO bits are connected to the U38 MSP430 system controller for general purpose
signaling or communicaons between the Zynq UltraScale+ RFSoC and the MSP430 system
controller. These signals are level-shied by TXS0108E U37. The connecons between the U38
system controller and the ZU67DR RFSoC are listed in following table.
Table 8: System Controller U38 GPIO Connections to
ZU67DR U1
Net Name
MSP430 U38
Pin Name
MIO38_PS_GPIO1 P1_6
MIO13_PS_GPIO2 P1_7
I2C Bus Topology Overview
I2C0 (MIO 14-15), I2C1 (MIO 16-17)
The following gure shows a high-level view of the I2C0 and I2C1 bus connecvity.
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 28
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