• Four single color LEDs (callout 23)
○ LED_0: DS54
○ LED_1: DS55
○ LED_2: DS56
○ LED_3: DS57
• One user pushbuon and a CPU reset PB switch (callouts 24 and 25)
○ GPIO_SW_PL: SW8
○ CPU_RESET: SW13
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU670 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
Power and Status LEDs
[Figure 2, area of callouts 17 and 18]
The following table denes the power and status LEDs. For user controlled GPIO LED details, see
User I/O.
Table 20: Power and Status LEDs
Ref. Des.
Schematic Net
Name
LED
Color
Description
DS1 MIO23_LED Green RFSoC U1 Bank 500 GPIO LED
DS2 PS_INIT_B Green/ Red Green: FPGA initialization was successful Red: FPGA initialization is in
progress
DS3 PS_DONE Green RFSoC U1 bit file download is complete
DS4 PS_RESET_B Red POR U5 asserts RESET_B low when any of the monitored voltages
(IN_) falls below its respective threshold, any EN_ goes low, or MR is
asserted.
DS5 PS_ERR_OUT Red PS error out is asserted for accidental loss of power, an error in the
PMU that holds the CSU in reset, or an exception in the PMU.
DS6 PS_ERR_STATUS Red PS error status indicates a secure lockdown state. Alternatively, it
can be used by the PMU firmware to indicate system status.
DS7 USB3 MIC2544 U7
FLG
Green PS USB 3.0 ULPI VBUS power error
P1-R ENET_LED_0 Green EPHY U33 link established (all speeds) (RJ45 bezel right)
DS8 ENET_LED_1 Green EPHY U33 1000BASE-T link established
P1-L ENET_LED_2 Green EPHY U33 link activity (RJ45 bezel left)
DS9 MSP430_LED0 Blue MSP430 U38 GPIO LED
DS10 MSP430_LED1 Green MSP430 U38 GPIO LED
DS19 VCC12_SW Green 12VDC power on
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 50
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