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Analog Devices AN-877 - Table of Contents; Revision History

Analog Devices AN-877
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AN-877 Application Note
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Introduction ................................................................................... 1
Definition ....................................................................................... 1
Revision History ............................................................................ 2
SPI Port Pins .................................................................................. 3
Serial Clock (SCLK) .................................................................. 3
Serial Data Input/Output (SDIO)............................................. 3
Chip Select Bar (CSB)................................................................ 3
Serial Data Out (SDO) .............................................................. 4
Format ............................................................................................ 5
Instruction Phase ....................................................................... 5
Read/Write ................................................................................. 5
Wo r d L e n gt h .............................................................................. 5
Streaming ................................................................................... 6
Address Bits................................................................................ 6
Detection of SPI Mode and Pin Mode ......................................... 7
Hardware Interfacing ................................................................ 7
Chip Programming........................................................................ 8
Configuration Register (0X000)................................................ 8
Transfer Register (Master-Slave Latching) (0x0FF) ................ 8
Chip ID (0x001)......................................................................... 9
Chip Grade (0x002) ................................................................... 9
Device Indexing (0x004 and 0x005)......................................... 9
Program Registers.................................................................... 10
Programming Example ............................................................... 17
Contro l Re gister........................................................................... 18
REVISION HISTORY
4/2017R e v. A to Rev. B
Change CSB 0 to CSB in Figure 1..................................................1
Changes to Figure 2 ........................................................................1
Change to Serial Clock (SCLK) Section........................................3
C h an g es to Ta b le 2 Ca pt io n ...........................................................6
Changes to Table 3 Caption ...........................................................8
C h an g es to Ta b le 4 and Table 5....................................................10
C h an g es to Ta b le 6 and Table 7....................................................11
C h an g es to Ta b le 8 ........................................................................12
Changes to Ta b le 9 ........................................................................13
Changes to Table 10 and Table 11................................................14
C h an g es to Ta b le 12 ......................................................................15
C h an g es to Ta b le 13 ......................................................................16
Change to Programming Example Section.................................17
C h an g es to Ta b le 14 ......................................................................18
4/2007Initial Version to Rev. A
Updated Format............................................................... Universal
Changes to Transfer Register Section............................................8
Changes to Figure 13 ....................................................................10
Added Table 6 ...............................................................................11
Added PLL Control (0x00A) Section ..........................................11
C h an g es to Ta b le 8 ........................................................................12
12/2005Revision 0: Initial Version