Application Note AN-877
Rev. B | Page 15 of 20
Bit 5 to Bit 0—Delay
Bit 5 to Bit 0 represent chip-specific offset timings, with 0x00
being the most negative adjustment and 3F being the most
positive.
Reference Adjust (0x018)
Register 0x018 allows the internal reference voltage to be
selected and/or adjusted.
Bit 7 to Bit 6—VREF Select
Bits[7:6] determine which V
REF
is used.
If set to:
• 00, the primary V
REF
is connected.
• 01, the secondary V
REF
is selected.
1× is reserved for additional reference options.
Bit 5 to Bit 0
Bit 5 to Bit 0 allow the internal V
REF
to be adjusted. The
adjustment range is specified in the device data sheet.
User Test Patterns (0x019 through 0x020)
These registers are used with test mode configurations allowing
the user to specify test patterns. These are paired registers with
0x019 paired with 0x01A, 0x01B with 0x01C, 0x01D with 0x01E,
and 0x01F with 0x020. The low address is the least significant
byte. (See the Output Test Modes (0x00D) section of this
application note.)
Serial Data Control Channel (0x021)
Register 0x021 is the high speed serial data control channel. It
may also be used in parallel output devices to control the
number of output bits that are active (Bit 2 to Bit 0).
Bit 7—LSB First
When this bit is set, devices using a serial port for the converter
data output, shift the data LSB first. If clear (default), the MSB is
shifted first.
Bit 6 to Bit 4—Reserved
Bit 3—PLL Optimize
Bit 3 is used to optimize PLL operations for various frequency
ranges (see the device data sheet for details).
Bit 2 to Bit 0
These bits are used to determine the number of bits shifted in
the serial frame or parallel output. If set to 000, the native
number of bits of the converter are shifted. This control allows
for both truncation and padding of the bit stream. For example,
a 12-bit converter can be forced to appear as an 8-bit converter
by setting the lower 3 bits of this register to 001. Likewise, the
same 12-bit converter can be forced to look like a 16-bit
converter by padding the extra bits with zeroes (support for the
full range of this setting is described in the device data sheet.
Not all options may be present on all devices).
Table 12. Output Frame Length, Register 0x021, Bits[2:0]
Bit 2 to Bit 0 Serial Output Frame Length
000 Native bit length
001 Truncate/fill to 8 bits
010 Tru ncate/f ill to 10 bits
101 Truncate/fill to 16 bits
110 Reserved
111 Reserved
Serial Channel Power-Down (0x022)
Serial channel power-down is used to control the state of each
serial channel in a serial output converter.
Bit 7 to Bit 2—Reserved
Bit 1—Channel Output Reset
When Bit 1 (CH_OUTPUT_RESET) is selected for either a data
channel or clock channel, everything is left powered up.
However, the output flip-flop, prior to the LVDS driver
associated with that channel is held in reset.
Bit 0—Channel Power-Down
When Bit 0 (CH_POWER_DOWN) is selected for a data
channel, the associated ADC and LVDS driver are powered
down while the associated digital circuitry is held in reset.
When Bit 0 (CH_POWER_DOWN) is selected for a clock
channel, the associated LVDS driver is powered down, and the
associated digital circuitry is held in reset.
MISR Registers (0x024 Through 0x025)
Register 0x024 is the multiple input signature register (MISR)
least significant byte. Register 0x025 is the MISR most
significant byte. The MISR is a multiple input signature register.
This register is used in conjunction with the BIST (0x00E). This
register is a mirror of the core MISR and is read only.
Features (0x02A)
Bit 7 to Bit 1—Reserved
Bit 0—Overrange Enable
When Bit 0 is set, the overrange pin is disabled. When clear, the
overrange operates normally.
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