Analog Devices AN-877 User Manual

AN-877
APPLICATION NOTE
One Technology Wa y • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Interfacing to High Speed ADCs via SPI
by the High Speed Converter Division
Rev. B | Page 1 of 20
INTRODUCTION
This application note describes how to use the serial peripheral
interface (SPI) port on Analog Devices, Inc., high speed converters.
In addition, this application note defines the electrical, timing,
and procedural requirements for interfacing to these devices.
The implementation is compatible with industry-standard SPI
ports and employs, at minimum, a 2-wire mode and optional
chip select.
DEFINITION
The SPI port consists of three pins: the serial clock pin (SCLK),
the serial data input/output pin (SDIO), and the chip select bar
pin (CSB). Optionally, some chips may implement a serial data
out pin (SDO), which is referred to as 3-wire mode. To minimize
pin count, most chips omit this pin. However, if it is included, it is
used only for reading data from the device.
CSB
SCLK
SCLK
SDIO
SDIO
CSB
SPI
CONTROLLER
CONVERTER
INTERFACE
05739-001
Figure 1. Single Device Control in 2-Wire Mode
05739-013
CSB 0
CSB 1
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
CSB
CSB
SPI
CONTROLLER
CONVERTER
INTERFACE
DEVICE 1
CONVERTER
INTERFACE
DEVICE 2
Figure 2. Multiple Device Control in 2-Wire Mode

Analog Devices AN-877 Specifications

General

Brand	Analog Devices
Model	AN-877
Category	Controller
Language	English

Summary

SPI Mode and Pin Control

SPI Mode vs. Pin Control Detection

Explains how CSB state determines SPI mode or alternate pin functions, and mode transition.

Hardware Interfacing Examples

Shows examples of interfacing with PIC microcontrollers and serial PROMs.

Chip Programming via SPI

Configuration Register (0x000) Details

Details bits for SDO activation, LSB/MSB first mode, and soft reset control.

Transfer Register (Master-Slave)

Describes the transfer register for synchronizing master and slave latches, and unbuffered registers.

SPI Register Details

Transfer Control and Chip Identification

Covers software/hardware transfer, Chip ID, Chip Grade, and Device Indexing registers.

Program Register Configuration

Modes and Clock Control Registers

Configures device modes, power-down states, PLL, clock boost, and duty cycle stabilizer.

Advanced SPI Configuration

PLL, Clock Divider, and Enhancement Modes

Built-In Self Test and Analog Input

Built-In Self Test (BIST) and Analog Input Config

Configures BIST for diagnostics and sets analog input bandwidth, disconnect, and common-mode options.

Offset and Gain Adjustment

Output Configuration and Timing

Output Mode and Logic Type Settings

Controls output logic type, multiplexer, enable, DDR, invert, and output coding.

Output Settings, Termination, and Delay Adjust

Serial Data Control and Channel Management

Filter and Input Configuration

High-Pass Filter and Analog Input Impedance

SPI Programming Example

Control Register Map Summary

Detailed Register Configurations

Output Mode, Timing, and Reference Settings