ARM DSTREAM-ST - Page 6

List of Figures
Arm
®
DSTREAM-ST System and Interface Design
Reference Guide
Figure 1-1 Simple JTAG connection ....................................................................................................... 1-13
Figure 1-2 Chained JTAG connection ..................................................................................................... 1-14
Figure 1-3 JTAG timing diagram ............................................................................................................. 1-15
Figure 1-4 Basic JTAG port synchronizer ............................................................................................... 1-16
Figure 1-5 Timing diagram for the Basic JTAG synchronizer .................................................................. 1-16
Figure 1-6 JTAG port synchronizer for single rising-edge D-type ASIC design rules ............................. 1-16
Figure 1-7 Timing diagram for the D-type JTAG synchronizer ................................................................ 1-17
Figure 1-8 Example reset circuit ............................................................................................................. 1-20
Figure 1-9 SWD timing diagrams ............................................................................................................ 1-22
Figure 1-10 TRACECLK timing diagram ................................................................................................... 1-25
Figure 1-11 Target interface logic levels ................................................................................................... 1-26
Figure 1-12 Input/Output signals ............................................................................................................... 1-28
Figure 1-13 TCK signal ............................................................................................................................. 1-28
Figure 1-14 Reset signals ......................................................................................................................... 1-28
Figure 1-15 Trace signals .......................................................................................................................... 1-29
Figure 1-16 VTREF signals ....................................................................................................................... 1-29
Figure 1-17 Typical SWD circuit ................................................................................................................ 1-30
Figure 1-18 Typical JTAG circuit ............................................................................................................... 1-31
Figure 2-1 Arm JTAG 20 connector pinout .............................................................................................. 2-34
Figure 2-2 CoreSight 10 connector pinout .............................................................................................. 2-35
Figure 2-3 CoreSight 20 connector pinout .............................................................................................. 2-36
Figure 2-4 TI JTAG 14 connector pinout ................................................................................................. 2-38
100893_0100_06_en Copyright © 2017–2019 Arm Limited or its affiliates. All rights
reserved.
6
Non-Confidential