Atari 400 Hardware Manual

IRQ Interrupts: IRQ interrupts are all "maskable" together by one bit
of the status register on the microprocessor. This bit is set to the
disable condition automatically by power turn on to prevent interrupt of
power turn on service routines.** In addition to this processor IRQ mask
bit, there are separate system IRQ interrupt enable bits for each IRQ
interrupt function (bits 0 thru 7 of IRQEN). These bits are not initialized
by power turn on, and must be initialized by the program before enabling the
processor IRQ. The 8 types of IRQ interrupts are:
D7 BREAK KEY (depression of the break key)
D6 OTHER KEY (depression of any other key)
DS = SERIAL INPUT READY (Byte of serial data has been received and is
ready to be read by the processor in SERIN register).
D4 SERIAL OUTPUT NEEDED (Byte of serial data is being transmitted and
SEROUT is ready to be written to again by the processor).
D3 TRANSMISSION FINISHED (serial data transmission is finished.
Output shift register is empty).
D2 TIMER #4 (audio divider #4 has counted down to zero)
D1 = TIMER #2 (audio divider #2 has counted down to zero)
DO TIMER #1 (audio divider #1 has counted down to zero)
In addition to the above IRQ interrupts (enabled by bits 0 through 7 of
IRQEN and identified by status bits 0 thru 7 of IRQST) there are two more
system IRQ interrupts which are generated over the serial bus Proceed and
Interrupt lines.
D7 of PACTL
DO of PACTL
D7 of PBCTL
DO of PBCTL
peripheral
peripheral
peripheral
peripheral
"A"
interrupt
"A"
interrupt
"B"
interrupt
"B"
interrupt
status
bit
enable bit
status bit
enable bit
These last two interrupts are automatically disabled ' by power turn on,
and their status bits are reset by reading from port A register and port B
register. (See PORTA, PACTL, PORTB, and PBCTL Register descriptions.)
The IRQEN register, like the NMIEN register, enables interrupts
when its bits are 1 (logic true). The IRQST however (unlike the NMIST) has
interrupt status bits that are normally logic true, and go to zero to
indicate an interrupt request. The IRQST status bits are returned to logic
true only by writing a zero into the corresponding IRQEN bit. This will
disable the interrrupt and simultaneously set the interrupt status bit to
one. Bit 3 of IRQST is not a latch and does not get reset by interrupt
disable. It is zero when the serial out is empty (out finished) and true
when it is not.
** - NOTE: An NMI also disables the I bit.
II.29

Atari 400 Specifications

General

Manufacturer	Atari
Model	400
Type	Home Computer
Release Year	1979
CPU	MOS Technology 6502
CPU Speed	1.79 MHz
ROM	10 KB
Operating System	Atari OS
Keyboard	Membrane keyboard
RAM	8 KB (expandable to 48 KB)
Graphics	ANTIC and GTIA chips
Sound	4 channels
Display	RF output for connection to TV
Storage	Optional cassette tape drive or floppy disk drive
Ports	Cartridge
Display Resolution	320x192 (16 colors)