Atari 400 Hardware Manual

High Pass Filters: The high pass filter consists of a "D" flip flop
and an exclusive-OR Gate. The noise control circuit output is sampled by
this flip flop at a rate set by the "High Pass" clock. The input and output
of the Flip Flop pass through the exclusive-OR Gate. If the flip flop input
is changing much faster than the clock rate, the signal will pass easily
through the exclusive-OR Gate. However, if it is lower than the clock rate,
the flip flop output will tend to follow the input and the two exclusive-OR
Gate inputs will mostly be identical (11 or 00) giving very little output.
This gives the effect of a crude high pass filter, passing noise whose
minimum frequency is set by the high pass clock rate. Only channels
1 and 2 have such a high pass filter. The high pass clock for channel 1
comes
from the channel 3 divider. The high pass clock for channel 2 comes
from the channel 4 divider. This filter is included only if bit 1 or 2 of
AUDCTL is true.
Volume Control: A volume control circuit is placed at the output of
each channel. This is a crude 4 bit digital to analog converter that
allows selection of one of 16 possible output current levels for a logic
true audio input. A logic zero audio input to this volume circuit always
gives an open circuit (zero current) output. The volume selection is
co nt rolled by bits 0 thru 3 of AUDCX. "Volume Control only" mode can be
invoked by forcing this circuit's audio input true with bit 4 of AUDCX. In
this mode the dividers, noise counters, and filter circuits are all discon-
nected from the channel output. Only the volume control bits (0 to 8 of
AUDCX) determine the channel output current.
The audio output of any channel can be completely turned off by writing
zero to the volume control bits of AUDCX. All ones gives maximum volume.
C. SERIAL PORT
The serial port consists of a serial data output (transmission)
line, a serial data input (receiver) line, a serial output clock line, a
bi-directional serial data clock line, and other miscellaneous control lines
described in the Operating System Manual. Data is transmitted and received
as 8 bits of serial data preceded by a logic zero start bit, and succeeded
by a logic true stop bit. Input and output clocks are equal to the baud
(bit) rate, not 16 times baud rate. Transmitted data changes when the
output clock goes true. Received data is sampled when the input c lock goes
to ze r o.
Serial Output: The transmission sequence begins when the processor
writes 8 bits of parallel data into the se rial output register (SEROUT ) (see
audio and serial port block diagram). When any previous data byte trans-
mission is finished the hardware will automatically transfer ~ data from
(SEROUT) to the output shift register, interrupt the processor to indicate
an emp t y (SEROUT) r egister (ready to be reloaded with the next byte of
data), and automatically serially transmit the shift register contents with
start-stop bits attached. If the processor responds to the interrupt, and
reloads SEROUT before the shift register is completely transmitted, the
serial transmission will be smooth and continuous.
II. 25

Atari 400 Specifications

General

Manufacturer	Atari
Model	400
Type	Home Computer
Release Year	1979
CPU	MOS Technology 6502
CPU Speed	1.79 MHz
ROM	10 KB
Operating System	Atari OS
Keyboard	Membrane keyboard
RAM	8 KB (expandable to 48 KB)
Graphics	ANTIC and GTIA chips
Sound	4 channels
Display	RF output for connection to TV
Storage	Optional cassette tape drive or floppy disk drive
Ports	Cartridge
Display Resolution	320x192 (16 colors)