Atari 400 Hardware Manual

Output data is normally transmitted as logic levels (+4V=true OV=False).
Data can also be transmitted as two tone information. This mode is selected
by bit 3 of SKCTL. In this mode audio channel 1 is transmitted in place of
logic true, and audio channel 2 in place of logic zero. Channel 2 must be
the lower tone of the tone pair.
The processor can force the data output line to zero (or to audio
channel 2, if in two tone mode) by setting bit 7 of SKCTL. This is required
to force a break (10 zeros) code transmission.
Serial Output Clock: The serial output data always changes when the
serial output clock goes true. The clock then returns to zero in the center
of the output data bit time.
The baud (bit) rate of the data and clock is determined by audio
channel 4 audio channel 2, or by the input clock, depending on the serial
mode selected by bits 4, 5, and 6 of SKCTL. (See chart at end of this
section.)
Serial Input: The receiving sequence begins when the hardware has
received a complete 8 bit serial data word plus start and stop bits. This
data is automatically transferred to the 8 bit parallel input register
(SERIN), and the processor is interrupted to indicate an input data byte
ready to read in SERIN. The processor must respond to this interrupt, and
read SERIN, before the next input data word reception is complete, otherwise
an input data "over-run" will occur. This over-run will be indicated by bit
5 of SKSTAT (if bit 5 of IRQST is not RESET (true) before next input complete),
and means input data has been lost. This bit should be tested whenever
SERIN is read. Bit 7 of SKSTAT should also be tested to detect frame errors
caused by extra (or missing) data bits.
Direct Serial Input: The serial data input line can be read directly
by the microprocessor if desired, ignoring the shift register, by reading
bit 4 of SKSTAT.
Bi-Directional Clock: This clock line is used to either receive a
clock from an external clock source for clocking transmitted or received
data, or is used to supply a clock to external devices indicating the
transmit or reception rate. This clock line direction is determined
by the serial mode selected by bits 4, 5, and 6 of SKCTL. (See mode chart
at the end of this section.) Transmitted data changes on the rising edge of
this clock. Received data is sampled on the trailing edge of this clock.
Asynchronous Serial Input: Unclocked serial data (at an approximately
known (+5%) rate) can be received in the asynchronous modes. The receive
(input) shift register is clocked by audio channel 4. Channels 3 and
4 should be used together (AUDCTL bit 3 = 1) for increased resolution.
In asynchronous modes, channels 3 and 4 are reset by each start bit at the
beginning of each serial data byte. This allows the serial data rate to be
slightly different from the rate set by channels 3 and 4.
II.26

Atari 400 Specifications

General

Manufacturer	Atari
Model	400
Type	Home Computer
Release Year	1979
CPU	MOS Technology 6502
CPU Speed	1.79 MHz
ROM	10 KB
Operating System	Atari OS
Keyboard	Membrane keyboard
RAM	8 KB (expandable to 48 KB)
Graphics	ANTIC and GTIA chips
Sound	4 channels
Display	RF output for connection to TV
Storage	Optional cassette tape drive or floppy disk drive
Ports	Cartridge
Display Resolution	320x192 (16 colors)