Common Features Description
Atmel 8051 Microcontrollers Hardware Manual 2-110
4316B–8051–02/04
generate an LCALL to the appropriate service routine, provided this hardware-
generated LCALL is not clocked by any of the following conditions:
1. An interrupt of equal or higher priority level is already in progress.
2. The current (polling) cycle is not the final cycle in the execution of the instruction
in progress.
3. The instruction in progress is RETI or any access to the IE or IP registers.
The polling cycle is repeated with each machine cycle, and the values polled are the
values that were present at S5P2 of the previous machine cycle. Note then that if an
interrupt flag is active but not being responded to for one of the above conditions, if the
flag is not still active when the blocking condition is removed, the denied interrupt will
not be serviced. In other words, the facts that the interrupt flag was once active but not
serviced is not remembered. Every polling cycle is new.
The polling cycle/LCALL sequence is illustrated in Figure 2-28.
Note that if an interrupt of higher priority level goes active prior to S5P2 of the machine
cycle labeled C3 in Figure 2-28, then in accordance with the above rules it will be
vectored to during CS and C6, without any instruction of the lower priority routine
having been executed.
Figure 2-28. Interrupt Response Timing Diagram
Thus the processor acknowledges an interrupt request by executing a hardware
generated LCALL to the appropriate servicing routine.
In some cases it also clears the flag that generated the interrupt, and in other cases it
doesn’t. It never clears the Serial Port or Timers 2 flags. This has to be done in the
user’s software. It clears an external interrupt flag (IEO or IE1) only if it was transition-
activated.
The hardware-generated LCALL pushes the contents of the Program Counter onto the
stack (but it does not save the PSW) and reloads the PC with an address that depends
on the source of the interrupt being vectored to, as shown below.
Table 2-23.
Source Vector Address
IE0 0003H
TF0 000BH
IE1 0013H
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