327
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
29.7 Two-wire Serial Interface Characteristics
Table 29-15 describes the requirements for devices connected to the 2-wire Serial Bus. The
ATmega48A/PA/88A/PA/168A/PA/328/P 2-wire Serial Interface meets or exceeds these requirements under the noted
conditions.
Timing symbols refer to Figure 29-5.
Table 29-15. Two-wire Serial Bus Requirements
Symbol Parameter
Condition Min. Max Units
V
IL
Input Low-voltage -0.5 0.3 V
CC
V
V
IH
Input High-voltage 0.7 V
CC
V
CC
+ 0.5 V
V
hys
(1)
Hysteresis of Schmitt Trigger Inputs 0.05 V
CC
(2)
–V
V
OL
(1)
Output Low-voltage 3mA sink current 0 0.4 V
t
r
(1)
Rise Time for both SDA and SCL 20 + 0.1C
b
(3)(2)
300 ns
t
of
(1)
Output Fall Time from V
IHmin
to V
ILmax
10pF < C
b
< 400pF
(3)
20 + 0.1C
b
(3)(2)
250 ns
t
SP
(1)
Spikes Suppressed by Input Filter 0 50
(2)
ns
I
i
Input Current each I/O Pin 0.1V
CC
< V
i
< 0.9V
CC
-10 10 µA
C
i
(1)
Capacitance for each I/O Pin – 10 pF
f
SCL
SCL Clock Frequency f
CK
(4)
> max(16f
SCL
, 250kHz)
(5)
0 400 kHz
Rp Value of Pull-up resistor
f
SCL
≤ 100kHz
f
SCL
> 100kHz
t
HD;STA
Hold Time (repeated) START Condition
f
SCL
≤ 100kHz 4.0 – µs
f
SCL
> 100kHz 0.6 – µs
t
LOW
Low Period of the SCL Clock
f
SCL
≤ 100kHz 4.7 – µs
f
SCL
> 100kHz 1.3 – µs
t
HIGH
High period of the SCL clock
f
SCL
≤ 100kHz 4.0 – µs
f
SCL
> 100kHz 0.6 – µs
t
SU;STA
Set-up time for a repeated START condition
f
SCL
≤ 100kHz 4.7 – µs
f
SCL
> 100kHz 0.6 – µs
t
HD;DAT
Data hold time
f
SCL
≤ 100kHz 0 3.45 µs
f
SCL
> 100kHz 0 0.9 µs
t
SU;DAT
Data setup time
f
SCL
≤ 100kHz 250 – ns
f
SCL
> 100kHz 100 – ns
t
SU;STO
Setup time for STOP condition
f
SCL
≤ 100kHz 4.0 – µs
f
SCL
> 100kHz 0.6 – µs
t
BUF
Bus free time between a STOP and START
condition
f
SCL
≤ 100kHz 4.7 – µs
f
SCL
> 100kHz 1.3 – µs
V
CC
0,4V–
3mA
----------------------------
1000ns
C
b
-----------------
V
CC
0,4V–
3mA
----------------------------
To Next Page
Loading...
Need help?
General
