328
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
Notes: 1. In ATmega48A/PA/88A/PA/168A/PA/328/P, this parameter is characterized and not 100% tested.
2. Required only for f
SCL
> 100kHz.
3. C
b
= capacitance of one bus line in pF.
4. f
CK
= CPU clock frequency
5. This requirement applies to all ATmega48A/PA/88A/PA/168A/PA/328/P 2-wire Serial Interface operation. Other devices con-
nected to the 2-wire Serial Bus need only obey the general f
SCL
requirement.
Figure 29-5. Two-wire Serial Bus Timing
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
SDA
t
r
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