ATtiny10/11/12
46
The device can be clocked by any clock option during Low-voltage Serial Programming. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 MCU clock cycles
High: > 2 MCU clock cycles
Low-voltage Serial Programming Algorithm
When writing serial data to the ATtiny12, data is clocked on the rising edge of SCK. When reading data from the ATtiny12,
data is clocked on the falling edge of SCK. See Figure 31, Figure 32 and Table 26 for timing details. To program and verify
the ATtiny12 in the serial programming mode, the following sequence is recommended (See 4 byte instruction formats in
Table 25
):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In accordance with the setting of CKSEL
fuses, apply a crystal/resonator, external clock or RC network, or let the device run on the internal RC oscillator.
In
some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET
must be
given a positive pulse of at least two MCU cycles duration after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable Serial instruction to the
MOSI (PB0) pin.
3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the
second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Whether the
echo is correct or not, all 4 bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a
positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is
no functional device connected.
4. If a Chip Erase is performed (must be done to erase the Flash), wait t
WD_ERASE
after the instruction, give RESET a
positive pulse, and start over from Step 2. See Table 27 on page 49 for t
WD_ERASE
value.
5. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the
appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written.
Use Data Polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait
t
WD_FLASH
or t
WD_EEPROM
before transmitting the next instruction. See Table 28 on page 49 for t
WD_FLASH
and
t
WD_EEPROM
values. In an erased device, no $FFs in the data file(s) needs to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the content at the selected
address at the serial output MISO (PB1) pin.
7. At the end of the programming session, RESET
can be set high to commence normal operation.
8. Power-off sequence (if needed):
Set XTAL1 to “0” (if external clocking is used).
Set RESET to “1”.
Turn V
CC
power off.
To Next Page
Loading...
Need help?
General
