Digital Counter / Timer / Tach User Manual, 1st Ed.
2-9
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1-Stage Counting (StA6E 1)
A single count setting value SV is available in 1-Stage Counting. Both Outputs 1 and 2 operate concurrently and
will turn ON momentarily for the time set in the output pulse width parameter (tout2) or will be maintained ON
depending on the Output Mode selected.
CTT Counter Functions
1-Stage Counting (StA6E 1)
Counting Down (down)
Counting Down (
down
)
With the input signal OFF at input CP2, each leading edge of the
input signal at CP1 will decrement the count present value PV by 1.
Turning ON the input signal at CP2, will prohibit the input signal
at CP1 from decrementing the PV.
Input Mode:
Mode F (
F
)
When the count present value PV counts down to 0 both
outputs 1 and 2 will turn ON. The count PV will continue to
decrement with each input signal.
The leading edge of a “reset” input signal at RST1 will turn
OFF both outputs, reset the count PV to the count setting
value SV, and prohibit an input signal from decrementing
the count PV. The trailing edge of the “reset” signal at RST1
enables counting to begin.
The “reset” signal minimum pulse width is set by reset pulse
width parameter (
rtSr
) or DIP Switch 8.
Output Modes:
Mode N (
n)
When the count present value PV counts down to 0 both
outputs 1 and 2 will turn ON. The count PV will remain at 0
regardless of additional input signals.
The leading edge of a “reset” input signal at RST1 will turn
OFF both outputs, reset the count PV to the count setting
value SV, and prohibit an input signal from decrementing
the count PV. The trailing edge of the “reset” signal at RST1
enables counting to begin.
The “reset” signal minimum pulse width is set by reset pulse
width parameter (
rtSr
) or DIP Switch 8.
A
Prohibit
A
n
n-1
n-2
n-3
n-4
n-5
H
L
H
L
CP1
CP2
0
Present
Value
CP1: Counter input prohibited CP2: Counter input
With the input signal ON at input CP1, each trailing edge of the
input signal at CP2 will decrement the count present value PV by 1.
Turning OFF the input signal at CP1, will prohibit the input signal
at CP2 from decrementing the PV.
999999
RESET
SV
OUT2
OUT1
PV
Stage 1
Input Mode DOWN