Digital Counter / Timer / Tach User Manual, 1st Ed.
1-800-633-0405
4-68
Timer + Counter Mixed Mode
In Timer + Counter Mixed Mode, timer period setting value SV1 controls Output 1 and counter setting value SV2
controls Output 2. Output 1(Timer) will turn ON momentarily for the time set in the output pulse width parameter
(
tout1
) or will be maintained ON (
tout1
set to 0.00). Output 2 (Counter) will turn ON momentarily for the
time set in the output pulse width parameter (
tout2
) or will be maintained ON depending on the output mode
selected.
Timer Mode - Repeat Cycle (
rCy
)
With power applied to the CTT, the leading edge of an input signal at START will begin the timing period setting
value SV1 timing up or down based on parameter (t modE). At the end of the timing period, the timing period will
reset and repeat automatically.
If the output pulse width parameter (
tout1
) is set to 0.00 Output 1 will turn ON at the end of the first timing
period, turn OFF at the end of the next timing period, turn ON at the end of the next timing period, etc.
If the output pulse width parameter (
tout1
) is set to >0.00 Output 1 will turn ON momentarily for the time set in
the output pulse width parameter (
tout1
) at the beginning of the each timing period.
The trailing edge of the “start” signal has no effect on the output or timing period.
The leading edge of a “reset” input signal at RST1 will turn OFF Output 1, reset the timing period and prohibit
the start of a new timing period. The “reset” signal minimum pulse width is set by reset pulse width parameter
(
rtSr
). The leading edge of a new “start” signal is necessary to restart the cycle.
The leading edge of an “pause” input signal at GATE will pause the timing period after it has been started. The
timing period will continue after the trailing edge of the “pause” (Gate) signal.
When power is removed, both outputs will turn OFF and the timing period will be reset.
Counter Input Mode:
Mode F (F)
When the count present value PV counts down to 0, Output 2
will turn ON. The count PV will continue to decrement with
each input signal.
The leading edge of a “reset” input signal at RST1 will turn
Output 2 OFF, reset the count PV to the count setting value
SV2, and prohibit an input signal from decrementing the count
PV. The trailing edge of the “reset” signal at RST1 enables
counting to begin.
The “reset” signal minimum pulse width is set by reset pulse
width parameter (
rtSr
).
Counter Output Modes:
Counter Input Mode - Counting Down (
down
)
Each leading edge of the input signal at CP1 will decrement the count present value PV by 1.
Timer+Counter Mixed Mode
OUT2
TIMER + COUNTER
Counter Input Mode DOWN
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