Digital Counter / Timer / Tach User Manual, 1st Ed.
2-23
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1-Stage Counting (
StA6E 1
)
A single count setting value SV is available in 1-Stage Counting. Both Outputs 1 and 2 operate concurrently and
will turn ON momentarily for the time set in the output pulse width parameter (
tout2
) or will be maintained ON
depending on the Output Mode selected.
CTT Counter Functions
1-Stage Counting (StA6E 1)
Quadrature (UdC)
Quadrature (
Ud C
)
When the quadrature input signal at CP1 changes before the input signal at CP2, the trailing edge of CP2
will increment the count present value PV by 1.
Input Mode:
Mode F (
F
)
When the count present value PV counts up to the count setting
value SV, both outputs 1 and 2 will turn ON. The count PV
will continue to increment or decrement with each input signal.
The leading edge of a “reset” input signal at RST1 will turn
OFF both outputs, reset the count PV to 0, and prohibit an
input signal from incrementing or decrementing the count PV.
The trailing edge of the “reset” signal at RST1 enables counting
to begin.
The “reset” signal minimum pulse width is set by reset pulse
width parameter (
rtSr
) or DIP Switch 8.
Output Modes:
Mode N (
n
)
When the count present value PV counts up to the count
setting value SV, both outputs 1 and 2 will turn ON. The count
PV will remain at the count SV regardless of additional input
signals.
The leading edge of “reset” input signal at RST1 will turn OFF
both outputs, reset the count PV to 0, and prohibit an input
signal from incrementing or decrementing the count PV. The
trailing edge of the “reset” signal at RST1 enables counting to
begin.
The “reset” signal minimum pulse width is set by reset pulse
width parameter (
rtSr
) or DIP Switch 8
When the quadrature input signal at CP2 changes before the input signal at CP1, the leading edge of CP2
will decrement the count present value PV by 1.
999999
RESET
SV
OUT2
OUT1
PV
Stage 1
Input Mode UdC
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