30-Oct-2020, Rev. 1.1
Table of Contents
1 INTRODUCTION .............................................................................................................................. 2
1.1 ZYNQ BANK PIN ASSIGNMENTS.................................................................................................... 5
2 FUNCTIONAL DESCRIPTION ......................................................................................................... 6
2.1 MEMORY – 1KB SHA SECURITY EEPROM – OPTIONAL ............................................................... 6
2.2 CLOCK SOURCE ............................................................................................................................ 6
2.3 RESET SOURCES ........................................................................................................................... 6
2.3.1 INIT# button – SW3 ............................................................................................................. 6
2.3.2 Power On Reset – POR# button – SW2 ................................................................................ 7
2.3.3 Processor Subsystem Reset: SYS_RST# button – SW4 .......................................................... 7
2.4 USER I/O ..................................................................................................................................... 8
2.4.1 User Push Buttons ............................................................................................................... 8
2.4.2 User LEDs ........................................................................................................................... 8
2.4.3 DIP Switches ....................................................................................................................... 8
2.5 INTERFACE HEADERS ................................................................................................................... 9
2.5.1 Digilent Pmod™ Compatible Expansion Headers (2x6) ...................................................... 9
2.5.2 JX1 and JX2 MicroZed interface microheaders ................................................................. 13
2.6 AGILE MIXED SIGNALING (AMS) INTERFACE ............................................................................. 19
2.6.1 XADC alternate GPIO function ......................................................................................... 20
2.7 JTAG CONFIGURATION.............................................................................................................. 22
2.8 POWER ...................................................................................................................................... 23
2.8.1 Power Input ....................................................................................................................... 23
2.8.2 Voltage Regulators ............................................................................................................ 24
2.8.3 Sequencing ........................................................................................................................ 24
2.8.4 Bypassing/Decoupling ....................................................................................................... 25
2.8.5 System Power Good LED .................................................................................................. 25
2.9 JUMPERS, CONFIGURATION AND TEST POINTS:............................................................................. 26
3 MECHANICAL ................................................................................................................................ 27
3.1 DIMENSIONS: ............................................................................................................................. 27
3.2 WEIGHT: .................................................................................................................................... 28
4 REVISION HISTORY ...................................................................................................................... 28