Avnet MicroZed - Jumpers, Configuration, and Test Points; Mechanical Specifications; IOCC Dimensions

30-Oct-2020, Rev. 1.1
26
2.9 Jumpers, configuration and test points:
The below table is a quick reference to all of the jumpers, configuration settings and test
points on the IOCC. For detailed information, refer to the appropriate sections in this
document.
Reference
Designator
Name Default Notes:
J1
PUDC#
Short 1-2 (disabled)
Active low.
J2
JTAG
Populated
Zynq JTAG interface.
J3
VBAT
Not Populated
JX1 pin 7. Zynq pin F11.
+1.8V for FPGA battery
support.
J4
Fan Header
Not Populated
Attached to Vin
J5
VCCIO_EN
Not Populated
Used to test the on-board
power supplies without a
MicroZed inserted.
J6
PG_CARRIER
Not Populated
Used to test the on-board
power supplies without a
MicroZed inserted.
DIP_SW0-3
DIP_SWx
In low position
4 user slide switches to
the Zynq PL fabric. Pulled
low. Active when high.
SW2
POR#
Open
Active low Power On
Reset signal. See section
2.3.2.
SW3
INIT#
Open
Active low initialization
signal. Rarely used. See
section 2.3.1.
SW4
CARRIER_SRST#
Open
Active low FPGA PS
reset. Interfaced with
JTAG J2. See section
2.3.3.
TP1
CARRIER_SRST
N/A
Signal monitor test point
TP2-5
GND
N/A
Power supply ground
TP6
A1V8
N/A
Analog +1.8V test point
TP7
VREF_1V25
N/A
+1.25V test point
TP8
VCCIO_34
N/A
VCCIO_34 test point
TP9
VCCIO_35
N/A
VCCIO_35 test point
TP10
3V3
N/A
+3.3V test point
CON3
VCCIO_34
Short 1-2
+3.3V setting for
VCCIO_34
CON4
VCCIO_35
Short 1-2
+3.3V setting for
VCCIO_35
BTN1-4
BTNx
Open
4 user input pushbuttons
to the Zynq PL fabric.
Pulled low, active high via
VCCIO_35 voltage setting
when depressed.
Table 21 - settings