30-Oct-2020, Rev. 1.1
2.5.2 JX1 and JX2 MicroZed interface microheaders
The Carrier features two MicroHeaders (TE PN: 5177984-4) for connection to
MicroZed. Each connector interfaces to Zynq PL I/O as well as eight PS-GPIO, six
dedicated analog inputs, and four dedicated JTAG signals.
*NOTE: the eight PS-GPIO and four JTAG signals are shared on MicroZed, thus for
each interface, it can only be used on either MicroZed or the Carrier, not
simultaneously.
• The connectors are FCI BERGSTAK 0.8mm pitch. These have variable stack
heights from 5mm to 20mm, making it easy to connect to a variety of
expansion or system boards.
• Each connector has 100 pins which include I/O, analog signals, as well as
power and ground. The Carrier powers the MicroZed as an alternative to the
USB-UART. Each pin can carry 500mA of current and has been tested and
certified against PCIe Gen2, thus sufficient bandwidth for this interface.
• MicroZed does not power the PL VCC
IO
banks, this is required by the Carrier.
This gives the Carrier the flexibility to control the I/O bank voltages. The
7Z010 has two PL I/O banks, banks 34 and 35, each containing 50 I/O.
• The 7Z020 has a third I/O bank, bank 13, which is powered on the IOCC by the
same supply as Bank35.
• Within a PL I/O bank, there are 50 I/O capable of 24 differential pairs.
Differential LVDS pairs on a -1 speed grade device are capable of 950Mbps of
DDR data. Each differential pair is isolated by a power or ground pin.
Additionally, eight of these I/O can be connected as clock inputs (four MRCC
and four SRCC inputs).
• Each PL bank can also be configured to be a memory interface with up to four
dedicated DQS data strobes and data byte groups. Bank 35 adds the capability
to use the I/O to interface up to 16 differential analog inputs. One of the
differential pairs in Bank 34 is not used as one of the pins is shared with
PUDC_B.
• The MicroZed with the Zynq 7Z020 populated has bank 13. While the bank
has 25 I/Os, only 15 of these signals are routed to the MicroHeader due to the
header’s pin limitations.
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