Avnet MicroZed - Page 15

30-Oct-2020, Rev. 1.1
14
Table 10 – Bank 13 Pins
Number of Pins
Name
Pin Number
1** VCCO_13
T8
U11
W7
Y10
1
IO_L6N_T0_VREF_13
V5
2
IO_L12P_T1_MRCC_13
IO_L12N_T1_MRCC_13
T9
U10
2
IO_L11P_T1_SRCC_13
IO_L11N_T1_SRCC_13
U7
V7
2
IO_L15P_T2_DQS_13
IO_L15N_T2_DQS_13
V8
W8
8
(Byte Group T3)
IO_L19P_T3_13
IO_L19N_T3_VREF_13
IO_L20P_T3_13
IO_L20N_T3_13
IO_L21P_T3_DQS_13
IO_L21N_T3_DQS_13
IO_L22P_T3_13
IO_L22N_T3_13
T5
U5
Y12
Y13
V11
V10
V6
W6
** With only one pin for VCCO_13, the PCB trace must be able to carry 500mA.
2.5.2.1 MicroHeader pinout assignments:
Table 11 – MicroHeader Pinout
MicroHeader #1 MicroHeader #2
Signal Name Source
Pin
Count
Signal Name Source
Pin
Count
PL
All Bank 34 Pins Zynq Bank 34 49
PL
All Bank 35
Pins
Zynq Bank 35 50
JTAG
TMS_0
Zynq Bank 0
5
P S
PS Pmod
MIO[0,9-15]
Zynq Bank
500
8
TDI_0
Zynq Bank 0
TCK_0
Zynq Bank 0
C
Init_B_0
Zynq Bank 0
2
TDO_0
Zynq Bank 0
Program_B_0
Zynq Bank 0
Carrier_SRST#
Carrier
Power
PG_Module
Module
1
Analog
VP_0
Zynq Bank 0
4
5V
Carrier
28
VN_0
Zynq Bank 0
GND
Carrier
DXP_0
Zynq Bank 0
VCCO_35
Carrier
3
DXN_0
Zynq Bank 0
Bank 13 pins
Bank 13 **
8
C
PUDC_B
Zynq Bank 34
2
Total
10
DONE
Zynq Bank 0
Power
PWR_Enable
Carrier
1
Power
Carrier
28
GND
Carrier
VCCO_34
Carrier
3
Bank 13 pins
Bank 13 **
8
TOTAL
100
** 7020 device only