PRINCIPLES OF OPERATION
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77
Chapter 8
Nearly ideal capacitors exist whereas high-gigohm resistors found in patch clamp
headstages possess intrinsic noise (in excess of thermal noise) and have limited
bandwidth due to stray capacitance. The benefits of capacitors are taken advantage
of in the PATCH configuration (capacitive feedback) of the Axopatch 200B
headstage, which is designed for ultra-low noise single-channel recordings. The
headstage measures the integral of the current which is subsequently differentiated
to allow measurement of the current itself. Unlike the resistive headstage, the
output of the capacitive headstage is fast. No boost circuit is required to increase
its high-frequency response. The capacitor mode achieves a substantial reduction
of noise and has much better linearity compared to resistive feedback headstages.
This noise reduction is particularly significant in the frequency band of interest for
single channel recordings (10 Hz - 10 kHz). In integrating headstages, the low-
frequency asymptote of the noise depends on the gate current of the headstage
input transistor rather than on the thermal noise of the feedback resistor. With the
U430 transistors used in the Axopatch 200B, this low frequency noise can be
substantially less than that of the 50 GΩ feedback resistor customarily used in
resistive headstages. At the same time, the high frequency noise is less because the
capacitor lacks the excess high frequency noise associated with gigohm value
resistors.
While the integrating headstage is quieter and more linear than resistive feedback
headstages there is one disadvantage. The voltage across the feedback capacitor
cannot ramp in one direction forever (the rate of change describes the current at the
input). At some point the capacitor voltage will approach the supply limits and the
integrator must be reset to start again near zero volts. Thus, the current record
must be interrupted for 50 µs while the integrator and differentiator reset. The
frequency of resets depends on the current that passes through the headstage, with
the larger current requiring more frequent resets.
When this reset occurs, a sample and hold circuit maintains the value of the current
at the level it had just prior to the reset. It does this for the duration of the reset
while the DATA NOT VALID line specifies that the reset is in progress.
Following reset, the sample and hold is inactivated, the DATA NOT VALID line
goes low and integration of the current again proceeds.
Figure 17 shows the signal pathway for the capacitor-feedback configuration. The
output current of the capacitor-feedback headstage is normally connected through a
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