SC01/SC02/SC11/SC12
Sc12hw09.doc page 6 of 37 24.11.1999 V0.9
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4. PIN FUNCTIONS
Pins That Are Used by Emulators
The following pins are used by emulators for debugging purposes: TxD0, RxD0
Pin Terminology
The following terms are used to describe the pins:
Input (I) - An input-only pin.
Output (O) - An output-only pin.
Input/Output (I/O) - A pin that can be either input or output.
Synchronous - Synchronous inputs must meet setup and hold times in relation to CLK.
Synchronous outputs are synchronous to CLK.
Asynchronous - Inputs or outputs that are asynchronous to CLK.
4.1 Address / Data bus
Pin Name Type Function
A[0..2] O Address Bus (output, three-state, synchronous)
These pins supply nonmultiplexed memory or I/O addresses to
the system one half of a CLK period earlier than the multiplexed
address and data bus (AD7–AD0). During a bus hold or reset
condition, the address bus is in a high-impedance state.
While the IPC@CHIP family microntroller directly interfacing
DRAM, A2–A0 will serve as the nonmultiplexed address bus for
external SRAM, FLASH, PROM, EPROM, and peripherals.
AD[0..7] I/O Multiplexed Address and Data Bus (input/output, three-
state, synchronous, level-sensitive)
These time-multiplexed pins supply partial memory or I/O
addresses, as well as data, to the system. This bus supplies the
low-order 8 bits of an address to the system during the first
period of a bus cycle (t1), and it supplies data to the system
during the remaining periods of that cycle (t2 , t3 , and t4). In 8-
bit mode, AD7–AD0 supplies the data for both high and low bytes.
The address phase of these pins can be disabled.
During a bus hold or reset condition, the address and data bus is
in a high-impedance state.
ALE O Address Latch Enable (output, synchronous)
This pin indicates to the system that an address appears on the
address and data bus (AD7–AD0). The address is guaranteed to
be valid on the trailing edge of ALE. This pin is three-stated during
ONCE mode.
ALE is three-stated and held resistively Low during a bus hold
condition. In addition, ALE has a weak internal pulldown resistor
that is active during reset, when it is enabled by software.
RD# O Read Strobe (output, synchronous, three-state)
This pin indicates to the system that the microcontroller is
performing a memory or I/O read cycle. RD is guaranteed to not
be asserted before the address and data bus is floated during the
address-to-data transition. RD floats during a bus hold condition.
WR# O Write Strobe (output, synchronous)
This pin indicates to the system that the data on the bus is to be
written to a memory or I/O device. WR floats during a bus hold or
reset condition.
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