SC01/SC02/SC11/SC12
Sc12hw09.doc page 8 of 37 24.11.1999 V0.9
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4.4 Interrupts
Pin Name Type Function
INT[0,2-4] I Maskable Interrupt Request (input,asynchronous)
These pins indicate to the microcontroller that an interrupt
request has occurred. If the INT pin is not masked, the
microcontroller transfers program execution to the location
specified by the corresponding INT vector in the microcontroller
interrupt vector table.
Interrupt requests are synchronized internally and can be edge-
triggered or level-triggered. To guarantee interrupt recognition,
the requesting device must continue asserting INT until the
request is acknowledged. INT2 becomes INTA when INT0 is
configured in cascade mode.
INTA# O Interrupt Acknowledge (output, synchronous)
When the microcontroller interrupt control unit is operating in
cascade mode, this pin indicates to the system that the
microcontroller needs an interrupt type to process the interrupt
request on INT0. The peripheral issuing the interrupt request
must provide the microcontroller with the corresponding interrupt
type.
PWD Pulse Width Demodulator (input, Schmitt trigger)
If pulse width demodulation is enabled, PWD processes a signal
through the Schmitt trigger. PWD is used internally to drive
TMRIN0 and INT2, and PWD is inverted internally to drive
TIMERIN1 and INT4. If INT2 and INT4 are enabled and timer 0
and timer 1 are properly configured, the pulse width of the
alternating PWD signal can be calculated by comparing the values
in timer 0 and timer 1.
In PWD mode, the signals TMRIN0, TMRIN1 and INT4 can be used
as PIOs. If they are not used as PIOs, they are ignored internally.
4.5 Timer
Pin Name Type Function
TMRIN[0..1] I Timer Input (input, synchronous, edge-sensitive)
These pins supply a clock or control signal to the internal
microcontroller timer 0 and 1. After internally synchronizing a
Low-to-High transition on TMRIN, the microcontroller increments
the corresponding timer. TMRIN must be tied High if not being
used. When PIO is enabled, TMRIN is pulled High internally.
TMRIN0 is driven internally by INT2/PWD when pulse width
demodulation mode is enabled. The TMRIN0 pin can be used as a
PIO when pulse width demodulation mode is enabled.
TMROUT[0..1] O Timer Output (output, synchronous)
These pins supplies the system with either a single pulse or a
continuous waveform with a programmable duty cycle. TMROUT is
floated during a bus hold or reset.
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