6. Tweaker Menu | 37
H510MH 2�0 | H510MX/E 2�0 | H510MH/E 2�0
tWR2RD_DG
This item delay between Write-to-Read commands in dierent Bank Group for DDR4. All other
DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
Opons: Auto (Default)
tWR2RD_DR
This item delay between Write-to-Read commands in dierent Ranks. 0-Auto, Range 4-54.
Opons: Auto (Default)
tWR2RD_DD
This item delay between Write-to-Read commands in dierent DIMMs. 0-Auto, Range 4-54.
Opons: Auto (Default)
tWR2WR_SG
This item delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range
4-54.
Opons: Auto (Default)
tWR2WR_DG
This item delay between Write-to-Write commands in dierent Bank Group for DDR4. All other
DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
Opons: Auto (Default)
tWR2WR_DR
This item delay between Write-to-Write commands in dierent Ranks. 0-Auto, Range 4-54.
Opons: Auto (Default)
tWR2WR_DD
This item delay between Write-to-Write commands in dierent DIMMs. 0-Auto, Range 4-54.
Opons: Auto (Default)
Advanced Timing Conguraon
tRDPRE
This item Holds DDR ming parameter tRDPRE. RD to PRE same bank minimum delay in DCLK
cycles. Supported Range is 6-15.
Opons: Auto (Default)