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Details revisions and dates of changes made to the TTCAN user manual.
Explains formatting conventions used throughout the TTCAN user manual.
Defines the purpose and target audience of the TTCAN user manual.
Lists related documents and specifications relevant to TTCAN.
Provides a high-level overview of the TTCAN IP module's architecture and features.
Illustrates the TTCAN module's internal components and their interconnections.
Lists the available interfaces for connecting TTCAN to controllers.
Explains the process of initializing the TTCAN CAN controller and message objects.
Describes how messages are transferred on the CAN bus after initialization.
Details how to disable automatic retransmission for TTCAN operation.
Explains entering Test Mode and writable test register functions.
Details the Test Register bits for various test functions.
Explains how to disable the TTCAN Application Watchdog.
Describes Silent Mode for bus monitoring without transmission.
Explains Loop Back Mode for hardware self-test.
Describes combining Loop Back and Silent Mode for self-testing.
Details the four output functions available for the CAN_TX pin.
Explains No Message RAM Mode for FPGA testing.
Explains register reset values and module behavior after hardware reset.
Lists registers controlling CAN Core operation and status.
Details bits for test, configuration, retransmission, and interrupts.
Explains bits for Bus_Off, warning, error passive, RxOk, TxOk, and LEC.
Describes how status interrupts are generated and handled.
Details Receive Error Counter and Transmit Error Counter.
Explains register bits for time segments and baud rate prescaler.
Describes extending the Baud Rate Prescaler for higher resolution.
Introduces IF1 and IF2 register sets for Message RAM access.
Specifies transfer direction and data selection for Message RAM access.
Explains registers for initiating message transfers and tracking progress.
Introduces Message Buffer registers mirroring Message Objects.
Details mask registers for acceptance filtering.
Describes registers for message identifier and direction.
Details control bits for message status, interrupts, and transmission.
Explains registers storing message data bytes.
Describes the structure of a Message Object in RAM.
Explains the Message Valid bit.
Explains the Use Acceptance Mask bit.
Explains the New Data bit.
Explains the Message Lost bit.
Explains the Receive Interrupt Enable bit.
Explains the Transmit Interrupt Enable bit.
Explains the Interrupt Pending bit.
Explains the Remote Enable bit.
Explains the Transmit Request bit.
Explains the Data Length Code.
Lists read-only registers providing status information.
Details the Interrupt Identifier for interrupt sources.
Shows registers holding transmission request bits for message objects.
Shows registers holding new data bits for message objects.
Shows registers holding interrupt pending bits for message objects.
Shows registers holding message valid bits for message objects.
Introduces registers specific to time-triggered communication.
Details the register for accessing the Trigger Memory.
Describes registers used for transferring data to/from Trigger Memory.
Explains bits for operation mode, time master, and priority.
Details register for expected Tx_Triggers in a matrix cycle.
Details register for reference message data length and Tx_Enable Window.
Explains the watchdog limit and its state bits.
Details enable bits for TT interrupts.
Describes the vector bits indicating specific interrupt sources.
Config Error bit.
Application Watchdog bit.
Watch Trigger bit.
Initialisation Watch Trigger bit.
Change of Error Level bit.
Tx_Count Overflow bit.
Tx_Count Underflow bit.
Global Time Error bit.
Global Time Discontinuity bit.
Global Time Wrap bit.
Stop Watch Event bit.
Time Mark Interrupt bit.
Start of Gap bit.
Change of Synchronisation Mode bit.
Start of System Matrix Cycle bit.
Start of Basic Cycle bit.
Details the Global Time value of the TTCAN network.
Explains the Cycle Time of the TTCAN basic cycle.
Details the Local Time of the TTCAN node.
Describes bits for ref trigger offset, wait for event, priority, sync state, and master state.
Explains the actual basic cycle count in the System Matrix.
Details registers for message status count and error level.
Details the low part of the TUR Numerator Configuration.
Details the TUR Denominator Configuration.
Explains the actual TUR Numerator value.
Details the Stop Watch register for timing events.
Details the register for presetting the Global Time.
Explains bits for sync deviation, clock speed, global time, and local time.
Time Mark Compare setting.
Disable External Time Mark Port.
External Clock Synchronisation control.
Stop Watch Source selection.
Wait for Global Time Discontinuity setting.
Set Global Time control bit.
Details the Sync_Mark captured at the Start of Frame.
Explains the register for time mark interrupts.
Details register bits for controlling time gaps in the schedule.
Explains the Message Handler FSM's tasks for data transfer.
Details the process of transferring data between registers and message RAM.
Describes message transmission in event-driven mode.
Explains how the TTCAN module filters incoming messages.
Details the process of storing received data frames.
Explains the handling of received remote frames.
Describes grouping message objects into FIFO buffers.
Explains message object priority based on message number.
Outlines module configuration steps after hardware reset.
Explains the importance and parameters of CAN bit timing configuration.
Details bit time division and bit rate configuration.
Explains the role of the propagation time segment in bit timing.
Details phase buffer segments and synchronisation mechanisms.
Discusses oscillator tolerance and its impact on bit timing.
Explains how the CAN Protocol Controller is configured using registers.
Guides the calculation of bit timing parameters.
Provides an example calculation for high baudrate bit timing.
Provides an example calculation for low baudrate bit timing.
Outlines subroutines for configuring message objects.
Shows the initialization for a transmit object for data frames.
Shows the initialization for a single receive object for data frames.
Explains configuring receive objects as FIFO buffers.
Shows the initialization for a single receive object for remote frames.
Describes TTCAN's operation after initialization and message handling.
Explains the common interrupt line and interrupt sources.
Describes how to update data bytes of a transmit object.
Explains dynamic management of transmit objects.
Details how to read received messages via IFx registers.
Explains using Remote Frames to request new data.
Describes clearing FIFO buffers by reading and resetting NewDat bits.
Details the initial setup and mode switching for TTCAN configuration.
Explains Network Time Unit (NTU), TUR, NumAct, DenomCfg, and drift compensation.
Details Time Master, priority, reference trigger offset, and time slaves.
Explains the Trigger Memory, its contents, and trigger types.
Discusses Message Status Count and configuration differences.
Details the configuration for the Reference Message.
Explains configuration for periodic transmit messages.
Details configuration for event-driven transmit messages.
Explains synchronisation to the TTCAN schedule.
Describes the behavior of Time Slaves during schedule initialisation.
Describes the behavior of Potential Time Masters during initialisation.
Discusses message reception and transmission in TTCAN.
Details handling of periodic messages.
Details handling of event-driven messages.
Explains gap control in Event Synchronised Time Triggered Operation.
Describes using the Stopwatch for timing external events.
Details time synchronization mechanisms and registers.
Summarizes TTCAN interrupts and error handling mechanisms.
Provides a configuration example for a TTCAN system with multiple nodes.
Explains the purpose of the Customer Interface for adapting signals.
Details the timing of the CAN_WAIT_B signal.
Describes the timing of the interrupt signal CAN_INT.
Lists all figures included in the document.
Details revisions and dates of changes made to the TTCAN user manual.
Explains formatting conventions used throughout the TTCAN user manual.
Defines the purpose and target audience of the TTCAN user manual.
Lists related documents and specifications relevant to TTCAN.
Provides a high-level overview of the TTCAN IP module's architecture and features.
Illustrates the TTCAN module's internal components and their interconnections.
Lists the available interfaces for connecting TTCAN to controllers.
Explains the process of initializing the TTCAN CAN controller and message objects.
Describes how messages are transferred on the CAN bus after initialization.
Details how to disable automatic retransmission for TTCAN operation.
Explains entering Test Mode and writable test register functions.
Details the Test Register bits for various test functions.
Explains how to disable the TTCAN Application Watchdog.
Describes Silent Mode for bus monitoring without transmission.
Explains Loop Back Mode for hardware self-test.
Describes combining Loop Back and Silent Mode for self-testing.
Details the four output functions available for the CAN_TX pin.
Explains No Message RAM Mode for FPGA testing.
Explains register reset values and module behavior after hardware reset.
Lists registers controlling CAN Core operation and status.
Details bits for test, configuration, retransmission, and interrupts.
Explains bits for Bus_Off, warning, error passive, RxOk, TxOk, and LEC.
Describes how status interrupts are generated and handled.
Details Receive Error Counter and Transmit Error Counter.
Explains register bits for time segments and baud rate prescaler.
Describes extending the Baud Rate Prescaler for higher resolution.
Introduces IF1 and IF2 register sets for Message RAM access.
Specifies transfer direction and data selection for Message RAM access.
Explains registers for initiating message transfers and tracking progress.
Introduces Message Buffer registers mirroring Message Objects.
Details mask registers for acceptance filtering.
Describes registers for message identifier and direction.
Details control bits for message status, interrupts, and transmission.
Explains registers storing message data bytes.
Describes the structure of a Message Object in RAM.
Explains the Message Valid bit.
Explains the Use Acceptance Mask bit.
Explains the New Data bit.
Explains the Message Lost bit.
Explains the Receive Interrupt Enable bit.
Explains the Transmit Interrupt Enable bit.
Explains the Interrupt Pending bit.
Explains the Remote Enable bit.
Explains the Transmit Request bit.
Explains the Data Length Code.
Lists read-only registers providing status information.
Details the Interrupt Identifier for interrupt sources.
Shows registers holding transmission request bits for message objects.
Shows registers holding new data bits for message objects.
Shows registers holding interrupt pending bits for message objects.
Shows registers holding message valid bits for message objects.
Introduces registers specific to time-triggered communication.
Details the register for accessing the Trigger Memory.
Describes registers used for transferring data to/from Trigger Memory.
Explains bits for operation mode, time master, and priority.
Details register for expected Tx_Triggers in a matrix cycle.
Details register for reference message data length and Tx_Enable Window.
Explains the watchdog limit and its state bits.
Details enable bits for TT interrupts.
Describes the vector bits indicating specific interrupt sources.
Config Error bit.
Application Watchdog bit.
Watch Trigger bit.
Initialisation Watch Trigger bit.
Change of Error Level bit.
Tx_Count Overflow bit.
Tx_Count Underflow bit.
Global Time Error bit.
Global Time Discontinuity bit.
Global Time Wrap bit.
Stop Watch Event bit.
Time Mark Interrupt bit.
Start of Gap bit.
Change of Synchronisation Mode bit.
Start of System Matrix Cycle bit.
Start of Basic Cycle bit.
Details the Global Time value of the TTCAN network.
Explains the Cycle Time of the TTCAN basic cycle.
Details the Local Time of the TTCAN node.
Describes bits for ref trigger offset, wait for event, priority, sync state, and master state.
Explains the actual basic cycle count in the System Matrix.
Details registers for message status count and error level.
Details the low part of the TUR Numerator Configuration.
Details the TUR Denominator Configuration.
Explains the actual TUR Numerator value.
Details the Stop Watch register for timing events.
Details the register for presetting the Global Time.
Explains bits for sync deviation, clock speed, global time, and local time.
Time Mark Compare setting.
Disable External Time Mark Port.
External Clock Synchronisation control.
Stop Watch Source selection.
Wait for Global Time Discontinuity setting.
Set Global Time control bit.
Details the Sync_Mark captured at the Start of Frame.
Explains the register for time mark interrupts.
Details register bits for controlling time gaps in the schedule.
Explains the Message Handler FSM's tasks for data transfer.
Details the process of transferring data between registers and message RAM.
Describes message transmission in event-driven mode.
Explains how the TTCAN module filters incoming messages.
Details the process of storing received data frames.
Explains the handling of received remote frames.
Describes grouping message objects into FIFO buffers.
Explains message object priority based on message number.
Outlines module configuration steps after hardware reset.
Explains the importance and parameters of CAN bit timing configuration.
Details bit time division and bit rate configuration.
Explains the role of the propagation time segment in bit timing.
Details phase buffer segments and synchronisation mechanisms.
Discusses oscillator tolerance and its impact on bit timing.
Explains how the CAN Protocol Controller is configured using registers.
Guides the calculation of bit timing parameters.
Provides an example calculation for high baudrate bit timing.
Provides an example calculation for low baudrate bit timing.
Outlines subroutines for configuring message objects.
Shows the initialization for a transmit object for data frames.
Shows the initialization for a single receive object for data frames.
Explains configuring receive objects as FIFO buffers.
Shows the initialization for a single receive object for remote frames.
Describes TTCAN's operation after initialization and message handling.
Explains the common interrupt line and interrupt sources.
Describes how to update data bytes of a transmit object.
Explains dynamic management of transmit objects.
Details how to read received messages via IFx registers.
Explains using Remote Frames to request new data.
Describes clearing FIFO buffers by reading and resetting NewDat bits.
Details the initial setup and mode switching for TTCAN configuration.
Explains Network Time Unit (NTU), TUR, NumAct, DenomCfg, and drift compensation.
Details Time Master, priority, reference trigger offset, and time slaves.
Explains the Trigger Memory, its contents, and trigger types.
Discusses Message Status Count and configuration differences.
Details the configuration for the Reference Message.
Explains configuration for periodic transmit messages.
Details configuration for event-driven transmit messages.
Explains synchronisation to the TTCAN schedule.
Describes the behavior of Time Slaves during schedule initialisation.
Describes the behavior of Potential Time Masters during initialisation.
Discusses message reception and transmission in TTCAN.
Details handling of periodic messages.
Details handling of event-driven messages.
Explains gap control in Event Synchronised Time Triggered Operation.
Describes using the Stopwatch for timing external events.
Details time synchronization mechanisms and registers.
Summarizes TTCAN interrupts and error handling mechanisms.
Provides a configuration example for a TTCAN system with multiple nodes.
Explains the purpose of the Customer Interface for adapting signals.
Details the timing of the CAN_WAIT_B signal.
Describes the timing of the interrupt signal CAN_INT.
Lists all figures included in the document.
General| Brand | Bosch |
|---|---|
| Model | TTCAN |
| Category | Network Hardware |
| Language | English |
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