■ BCM5221 Product Application Note
■ BCM5220 7/7/00
Broadcom Corporation
Page 5 5221/5220-AN01 Product Application Note, Revision R
PHYAD4/CK25. Physical Address input which, along with the other 4 PHYAD pins, sets a unique address for this device
to allow MDIO access. The CK25 output is a buffered version of REF_CLK for general use.
PHYAD3/PAUSE. Physical Address input which, along with the other 4 PHYAD pins, sets a unique address for this device
to allow MDIO access. The PAUSE output is an active low indication of the Flow Control capability of the far-end link partner
(logic 0 = link partner supports PAUSE, logic 1 = link partner does not support PAUSE). The state of this output is determined
by the result of auto-negotiation.
PHYAD2/ACT_LED#. Physical Address input which, along with the other 4 PHYAD pins, sets a unique address for this
device to allow MDIO access. The ACT_LED# output is an active low indication of packet activity (transmit and receive)
through the BCM5221 (logic 0 = activity, logic 1 = idle). If the use of this LED output is required, Broadcom recommends that
PHYAD2 be strapped high since the LED output polarity is active low.
PHYAD1/COL_LED#. Physical Address input that, along with the other 4 PHYAD pins, sets a unique address for this de-
vice to allow MDIO access. The COL_LED# output is an active low indication of collision and only meaningful during half
duplex operation (logic 0 = collision, logic 1 = no collision). If the use of this LED output is required, Broadcom recommends
that PHYAD1 be strapped high because the LED output polarity is active low.
PHYAD0/FDX_LED#. Physical Address input which, along with the other 4 PHYAD pins, sets a unique address for this
device to allow MDIO access. The FDX_LED# output is an active low indication of the current duplex state of the BCM5221
(logic 0 = Full Duplex, logic 1 = Half Duplex). If the use of this LED output is required, Broadcom recommends that PHYAD0
be strapped high because the LED output polarity is active low.
SPDLED#/ADV_PAUSE#. Active LED output that indicates the current operating speed of the BCM5221 (logic 0 = 100
MBps, logic 1 = 10 Mbps). The ADV_PAUSE# active low input allows the local MAC to directly indicate to the BCM5221 it’s
ability to support flow control. A logic 0 will set bit 10 in register 04h. A logic 1 clears bit 10 in register 04h.
100BASE-FX
The BCM5221 supports 100BASE-FX operation via the SD+/-, RD+/-, and TX+/- pins. The connection diagrams in Figure 3
on page 6 illustrate the proper termination and level shifting required to interface the BCM5221 to a 3.3V fiber transceiver.
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