7. Circuit Description
Amplifier
The 2016 amplifier includes a differential input stage for polarity selection, followed
by a differentiator, three low noise gain amplifier stages, three complex-pole ac
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tive-filter stages (optimized for improved pulse symmetry), a gated active baseline re
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storer and a unipolar output amplifier providing semi-Gaussian or semi-triangular
output pulse shaping. A bipolar stage is provided for SCA timing.
Input Amplifier
Gain amplifier 1 (schematic sheet 1) is a discrete low noise differential amplifier com
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prised of transistors Q1 through Q5, Q7, Q28 and Q29. This amplifier’s gain is se
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lected by the coarse gain switch and relay K1 and is X1 for a coarse gain of 5 and X2
for coarse gains of 10 and higher. Polarity is selected by having the input signal drive
Q29(+) or Q28 (–). The negative-going output signal provided by this stage drives the
pole/zero circuit and the first differentiator.
Differentiator and Gain Stages
The input amplifier’s output signal is differentiated by C13 through C18A and resistor
R25 (schematic sheet 2). The pole/zero compensation is performed by potentiometer
RV3 and resistors R45 through R49 and R26. The time constants are selected by sec-
tions of the shaping switch.
The differentiated and pole/zero compensated signal is amplified by gain AMPs 2
(A1), 3 (A2) and 4 (A3) or gain AMPs 2 and 4, depending on the COARSE GAIN
switch selection (schematic sheets 1 and 3). FINE GAIN and SFG (Super Fine Gain)
are performed in concert with gain AMP 2 and potentiometers RV8 and RV1 respec
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tively. The gain adjustment range of gain AMPs 2 through 4 are continuously adjust
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able from X2.5 to X750. Limiters in the feedback path of each amplifier eliminate
op-amp saturation maintaining good overload recovery. The output signal of gain
AMP 4 is normally negative and drives the FAST DISCriminator circuits and active
integrators A4, A5 and A6
25
Amplifier
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