Cisco UCS C480 M5 Memory Guide
Memory Configurations and Modes
7
DCPMM Guidelines
DCPMMs require second generation Intel Xeon Scalable Family processors. First generation Xeon Scalable
processors do not support DCPMMs.
All installed DCPMMs must be the same size. Mixing DCPMMs of different capacities is not supported.
DCPMMs and DIMMs must be populated as shown in Table 2 (6 DIMMs per CPU with 2, 4, or 6 DCPMMs per
CPU, as shown).
Table 2 2
nd
Generation Intel
®
Xeon
®
Scalable Processor DIMM and DCPMM
1
Physical Configurations (quad
socket)
DIMM
to
DCPMM
Count
CPU 1 (lower bay)
iMC1 iMC0
Channel 2 Channel 1 Channel 0 Channel 2 Channel 1 Channel 0
F2 F1 E2 E1 D2 D1 C2 C1 B2 B1 A2 A1
6 to 2 DIMM DIMM DCPMM DIMM DIMM DIMM DCPMM DIMM
6 to 4 DIMM DCPMM DIMM DCPMM DIMM DIMM DCPMM DIMM DCPMM DIMM
6 to 6 DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM
DIMM
to
DCPMM
Count
CPU 2 (lower bay)
iMC1 iMC0
Channel 2 Channel 1 Channel 0 Channel 2 Channel 1 Channel 0
M2 M1 L2 L1 K2 K1 J2 J1 H2 H1 G2 G1
6 to 2 DIMM DIMM DCPMM DIMM DIMM DIMM DCPMM DIMM
6 to 4 DIMM DCPMM DIMM DCPMM DIMM DIMM DCPMM DIMM DCPMM DIMM
6 to 6 DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM
DIMM
to
DCPMM
Count
CPU 3 (upper bay)
iMC1 iMC0
Channel 2 Channel 1 Channel 0 Channel 2 Channel 1 Channel 0
F2 F1 E2 E1 D2 D1 C2 C1 B2 B1 A2 A1
6 to 2 DIMM DIMM DCPMM DIMM DIMM DIMM DCPMM DIMM
6 to 4 DIMM DCPMM DIMM DCPMM DIMM DIMM DCPMM DIMM DCPMM DIMM
6 to 6 DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM