Clevo E4120 - Clock Generator

Schematic Diagrams
Clock Generator B - 3
B.Schematic Diagrams
Clock Generator
Sheet 2 of 40
Clock Generator
CLOCK GENERATOR
100MHz100MHz1(0.7V-1.5V)
0(default)
PI N _ 30 C P U_ 1CPU_0
133MHz133MHz
R133 10K_04
CPU_SEL_During CK_PEWGD Latch Pinl
CLK_SDATA
CLK_SCLK
CLK_P W RGD
SMBus
C LK_SD ATA
C LK_SC LK
3.3VS
SMB_DATA15
SMB_CLK15
C LK_SD ATA 10,11
C LK_SC LK 10 ,11
XOUT
L15 *15m il_short_06
L 1 4 * 1 5m i l _s h or t _0 6
3.3V 3,4,12,14,15,16,18, 19,20,21,23,24,25,29,30,31,33,34,35
RE F_0 /CP U_ SEL
5VS
S D
G
Q11A
MTDN 7002ZHS6R
2
6 1
REF_0/CPU_SEL
S D
G
Q11B
MTDN 7002ZHS6R
5
3 4
0.1uF near the every power pin
CLKGEN POWER
0.1uF near the every power pin
VDD_I/O can be
ranging from
1.05V to 3.3V
5VS 13,17,20,21,26,27,30,31,35,36
EMI Capactior
EMI
XIN
I C S 9 L RS 3 1 97
R e al t e k R T M8 7 5 N6 3 2 -V B
C213
0.1u_10V_X7R_04
R145
10K_04
C215
1u_6.3V_X5R_04
X1 FSX8L_14.31818MH z
12
C207
33p_50V_NPO_04
R142
1M_04
C208
33p_50V_N PO_04
Q12
M TN7 00 2 Z HS3
G
DS
C214
0.1u_10V_X7R_04
C204
1u_6.3V_X5R _04
C205
0.1u_10V_X7R _04
CPU_ STOP#
REF_ 0 /CPU _SE L C202 *10p_50V_NPO _06
U7
SLG8SP5 85
VDD _DOT
1
VDD _27
5
VDD _SRC
17
VDD _CPU
24
VDD _REF
29
VSS_DO T
2
XTAL_OU T
27
XTAL_IN
28
REF_ 0 /CPU _ SEL
30
SDA
31
SCL
32
VSS_2 7
8
VSS_SATA
9
VSS_SRC
12
VSS_CPU
21
VSS_REF
26
VD D_ SRC _I/O
15
VD D_ CPU _I/O
18
DOT_96
3
DOT_96#
4
27M
6
27M_SS
7
SRC_1/SATA
10
SR C_1# /SAT A#
11
SRC_ 2
13
SRC _2 #
14
CPU_STOP#
16
CPU_ 1
20
CPU _1 #
19
CPU_ 0
23
CPU _0 #
22
CKPWR GD /PD#
25
GN D
33
3.3VS
CLK_ VCC2CLK_VCC1
CLK_VCC 2
3.3VS
CLK_ VCC 1
1.1V S_VTT
3.3VS
3.3VS
C LK_BU F_DOT96_N 15
C LK_BU F_R EF1415
C LK_BU F_DOT96_P 15
C LK_BU F_BCLK_N 15
C LK_BU F_BCLK_ P 15
1.1VS_V TT 4,6, 7,14,15,16,19,20,21,34,35,36
3.3VS 10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,31,35,36
C LK_SATA 15
C LK_PC IE_ICH# 15
C LK_PC IE_ICH 15
CLKEN#36
C LK_SATA# 15
XOU T
XIN
R130 33_04
RN15
2.2K_4P2R _04
1 4
2 3
R 1 44 2. 2 1 K _1 % _ 04
R132 *4.7K_04