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Clevo E4120 - Battery Life Management

Clevo E4120
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Schematic Diagrams
B - 20 IBEXPEAK - M 6/9
B.Schematic Diagrams
IBEXPEAK - M 6/9
R350 * 10K _04
HOST_ALERT#1
R351 * 10K _04
SMI #
SC I #
R267 * 0_04
R254 * 10K_04
R274 10K_04
R272 10K_04
R253 56_04
LOW: DGPU PRESENT
DGPU_PRSNT#
BIOS_REC
DGPU_PRSNT #
STP_PCI#
SPI_CS#2 R257 56_04
GPIO
MISC
NCTF
RSVD
CPU
U20F
Ibex Peak-M_Rev0_9
GPIO27
AB12
GPIO28
V13
MEM_LED / GPIO24
H10
GPIO57
F8
LAN _PH Y_ P WR_CTRL / GPIO12
K9
V SS_ N CTF_1
A4
V SS_ N CTF_2
A49
V SS_ N CTF_3
A5
V SS_ N CTF_4
A50
V SS_ N CTF_5
A52
V SS_ N CTF_6
A53
V SS_ N CTF_7
B2
V SS_ N CTF_8
B4
V SS_ N CTF_9
B52
V SS_ N CTF_10
B53
V SS_ N CTF_11
BE1
V SS_ N CTF_12
BE53
V SS_ N CTF_13
BF1
V SS_ N CTF_14
BF5 3
V SS_ N CTF_15
BH 1
V SS_ N CTF_16
BH 2
V SS_ N CTF_17
BH 5 2
V SS_ N CTF_18
BH 5 3
V SS_ N CTF_19
BJ 1
V SS_ N CTF_20
BJ 2
V SS_ N CTF_21
BJ 4
V SS_ N CTF_22
BJ 4 9
V SS_ N CTF_23
BJ 5
V SS_ N CTF_24
BJ 5 0
V SS_ N CTF_25
BJ 5 2
V SS_ N CTF_26
BJ 5 3
V SS_ N CTF_27
D1
V SS_ N CTF_28
D2
V SS_ N CTF_29
D53
V SS_ N CTF_30
E1
V SS_ N CTF_31
E53
TACH2 / GPIO6
D37
TACH0 / GPIO17
F38
TACH3 / GPIO7
J32
TP9
M18
TP10
N18
TP11
AJ24
TP12
AK41
SATA3GP / GPIO37
AB13
SATA5GP / GPIO49
AA4
SCLOCK / GPIO22
Y7
SLOAD / GPIO38
V3
SDATA OUT0 / GPIO39
P3
SDATA OUT1 / GPIO48
AB6
A20GATE
U2
PR O CPW RGD
BE10
RCIN#
T1
PECI
BG10
THRMTRIP#
BD10
GPIO8
F10
CLKOUT_PCI E6N
AH45
CLKOUT_PCIE6P
AH46
PCIECLKRQ6# / GPIO45
H3
CLKOUT_PCI E7N
AF48
CLKOUT_PCIE7P
AF47
PCIECLKRQ7# / GPIO46
F1
TP5
AY46
TP4
AY45
TP6
AV43
TP7
AV45
BMBU SY # / G PIO 0
Y3
TP16
M30
TP17
N30
NC_1
AB45
NC_2
AB38
NC_3
AB42
NC_4
AB41
GPIO15
T7
TACH1 / GPIO1
C38
TP13
AK42
TP3
BB22
TP1
BA22
TP2
AW22
TP14
M32
TP15
N32
SATA2GP / GPIO36
AB7
NC_5
T39
INI T3_3V#
P6
STP_PCI# / GPIO34
M11
SATACLKREQ# / GPIO35
V6
SATA4GP / GPIO16
AA2
TP24
C10
TP8
AF13
CLKOUT_BCLK0_N / CLKOUT_PC I E8N
AM3
CLKOUT_BCLK0_P / CLKOUT_P CIE 8P
AM1
TP19
AA23
TP18
H12
R269
*0_04
R102
*0_04
R95 10K_04
R103 * 10K _04
R276
100K_04
R126 10K _04
R277 * 10K _04
R101 10K_04
R100
*0_04
R107 1K_04
R270 1K_1%_04
3.3V
3.3VS
3.3VS
1.1VS_VTT
3.3V S
3.3VS
3.3VS
1.1VS_VTT
3.3VS
3.3VS
SMI#28
GA20 28
SC I #28
H_PECI4,28
KBC _ RST# 28
BCLK_CPU_P4
BCLK_CPU_N4
3.3VS2,10,11, 12,13,14, 15,16,17,18, 20,21, 23,24,25, 26,27,28,29, 30,31,35, 36
H_ C PU PWRGD 4
H_THRMTR I P# 4
SB_BL O N12
1.1VS_VTT2, 4,6,7, 14,15,16,20, 21,34,35, 36
3.3V3,4,12, 14,15,16,18, 20,21, 23,24,25, 29,30,31, 33,34,35
CRI T_ TEMP_REP#3
PC H _MU TE#27
DRAMRST_CTRL4,9
R349 *10K_04
3.3V
DRAMRST_CTRL
C R B_SV_ D ET
CRIT_TE MP_R EP# _ R
MFG_MODE
C R B_SV_ D ET
MFG_MODE
S V_ SET_ U P
DGPU_PRSNT#
3.3VS
3.3VS
HOST_ALERT#1
GPIO35
PCH_GPIO57
BIOS RECOVERY
DISABLE----NO STUFF (DEFAULT)
ENABLE-----STUFF
BIOS_REC
RN21
10K_8P4R _04
1
2
3
4 5
6
7
8
Connected to PCH (THRMTRIP#)
Routing guidelines available in
Calpella Design Guide.
NOTE: CRB uses a 54.9 O ? %
series resistor and 56-O pull-up.
0213 S_GPIO CHANGE TO EDP_CARD_DET#
STP_ P CI#
SB_BLON
R352 * 1K_04
3.3VS
GPIO35
RN4
10K_8P4R _04
1
2
3
4 5
6
7
8
RN9
10K_8P4R _04
1
2
3
4 5
6
7
8
SPI _ C S#2
S V_ SET_ U P
PCH_MUTE#
SMI#
DRAMRST_CTRL
DGPU HDP (NV CONTROL BYSELF)
DGPU_HPD_INTR#
R258 0_04
DGPU_HPD_INTR#
IBEXPEAK - M (GPIO,VSS_NCTF,RSVD)
CRB/SV DETECT
NO STUFF [DETECT]
PCH_MUTE#
SCI#
H _ PEC I _R
EDP_ C AR D_DET#
CRI T _ TEM P_ R EP#_ R
EDP_ C AR D_DET#
Sheet 19 of 40
IBEXPEAK - M 6/9

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