5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
㫉
, 3.3V I/O.
L: Auto test disable & input offset cancellation enable
(default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable
Automatic EQ disable; Internal pull down at
~150K
㫉
, 3.3V IO
L: Automatic EQ enable (default)
H: Automatic EQ disable
㫉
,
3.3V I/O.
L: default, LEQ, compensate channel loss up to11.5dB @ HBR2
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
Port switching control or priority configuration;
Internal pull down at ~150K
㫉
, 3.3V I/O.
L: Port1 is selected or with higher priority (default)
H: Port2 is selected or with higher priority
Chip operational mode configuration;
Internal pull down at ~150K
㫉
, 3.3V
I/O.
L: Control switching mode (default)
H: Automatic switching mode
3 Levels Input:
L: Low
H: High
M: VDD33/2, connect both
pull-up and pull-down resistors
月
PS8338B
PD PIN:
L:Normal operation(default)
H:Chip power down
From Intel
Separate DDC/AUX
To TBT
To MDP CON
To TBT
To mDP
From Intel
L:mDP H:TBT
3 inch 0 via,
2 inch 1
ᾳ
via (4 lane
悥 忶
via),
data lane not swap.
DIFF=100ohm,
DIFF=100ohm,
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS 3.3VS
3.3VS
3.3VS
MUX_HPD3,19
OUT2_AUXn_SDA 20
OUT2_AUXp_SCL 20
MDP_CTRLCLK3,19
MDP_CTRLDATA3,19
MDP_D#33,19
MDP_D33,19
MDP_D#23,19
MDP_D23,19
MDP_D#13,19
MDP_D13,19
MDP_D#03,19
MDP_D03,19
PS8338B_PCH7
PS8338B_SW7
OUT2_D0p 20
OUT2_D0n 20
OUT2_D1p 20
OUT2_D1n 20
OUT2_D2p 20
OUT2_D2n 20
OUT2_D3p 20
OUT2_D3n 20
OUT2_HPD 20
OUT1_D3n 19
OUT1_D3p 19
OUT1_D2n 19
OUT1_D2p 19
OUT1_D1n 19
OUT1_D1p 19
OUT1_D0n 19
OUT1_D0p 19
OUT1_HPD 19
MDP_MODE 19
MDP_AUX3,19
MDP_AUX#3,19
OUT1_AUXn_SDA 19
OUT1_AUXp_SCL 19
Title
Size Document Number Rev
Date: Sheet
of
6-71-N15Z0-D01
D01
[18] PS8338B
A3
18 46Wednesday, August 29, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N150ZU
Title
Size Document Number Rev
Date: Sheet
of
6-71-N15Z0-D01
D01
[18] PS8338B
A3
18 46Wednesday, August 29, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N150ZU
Title
Size Document Number Rev
Date: Sheet
of
6-71-N15Z0-D01
D01
[18] PS8338B
A3
18 46Wednesday, August 29, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N150ZU
C240 0.1u_10V_X5R_04 W/TBT
R295
*4.7K_04 W/TBT
R307
*4.7K_04 W/TBT
R281
4.99K_1%_04
W/TBT
C224 0.1u_10V_X5R_04
W/TBT
R310
*4.7K_04 W/TBT
C239 0.1u_10V_X5R_04 W/TBT
R309
*4.7K_04 W/TBT
R314
100K_04
W/TBT
C230 0.1u_10V_X5R_04
W/TBT
R308
*4.7K_04 W/TBT
R282 *4.7K_04
W/TBT
R515 *4.7K_04
W/TBT
C267
0.01u_16V_X7R_04
W/TBT
C225 0.1u_10V_X5R_04
W/TBT
R291 *4.7K_04
W/TBT
R293
*4.7K_04 W/TBT
R294
*4.7K_04 W/TBT
C420
0.1u_6.3V_X5R_02
W/TBT
R315
100K_04
W/TBT
C428
0.1u_6.3V_X5R_02
W/TBT
C227 0.1u_10V_X5R_04
W/TBT
R512
*4.7K_04
W/TBT
C241
2.2u_6.3V_X5R_04
W/TBT
C223 0.1u_10V_X5R_04
W/TBT
C229 0.1u_10V_X5R_04
W/TBT
C419
0.01u_16V_X7R_04
W/TBT
R305
100K_04
W/TBT
C228 0.1u_10V_X5R_04
W/TBT
R306
100K_04
W/TBT
R292
*4.7K_04 W/TBT
C253
0.1u_6.3V_X5R_02
W/TBT
U10
PS8338B
W/TBT
PI1/SCL_CTL
1
I2C_CTL_EN
2
IN_HPD
3
IN_CA_DET
4
VDD33
5
IN_D0p
6
IN_D0n
7
PEQ
8
IN_D1p
9
IN_D1n
10
GND
11
IN_D2p
12
IN_D2n
13
PD
14
IN_D3p
15
IN_D3n
16
CEXT
17
SW
18
GND
19
REXT
20
VDD33
21
IN_DDC_SCL
22
IN_DDC_SDA
23
IN_AUXp
24
IN_AUXn
25
OUT1_AUXp_SCL
26
OUT1_AUXn_SDA
27
OUT2_AUXp_SCL
28
OUT2_AUXn_SDA
29
VDD33
30
OUT2_D3n
31
OUT2_D3p
32
OUT2_CA_DET
33
OUT2_D2n
34
OUT2_D2p
35
OUT2_D1n
36
OUT2_D1p
37
OUT2_HPD
38
OUT2_D0n
39
OUT2_D0p
40
OUT1_D3n
41
OUT1_D3p
42
OUT1_CA_DET
43
OUT1_D2n
44
OUT1_D2p
45
OUT1_D1n
46
OUT1_D1p
47
OUT1_HPD
48
OUT1_D0n
49
OUT1_D0p
50
VDD33
51
GND
52
PC21
53
PC20
54
PC11
55
PC10
56
VDD33
57
CFG1
58
CFG0
59
PI0/SDA_CTL
60
EPAD
61
R513
*4.7K_04
W/TBT
C226 0.1u_10V_X5R_04
W/TBT
R514 *0_04
W/TBT
PI0
PS8338B_CFG0
PC11
PC20
PC21
PC10
PS8338B_PEQ
IN_D2n
IN_D2p
IN_D1n
IN_D1p
PS8338B_PEQ
IN_D0n
IN_D0p
IN_ CA_DET
PI0
PS8338B_SW
PS8338B_CFG0
IN_D3n
IN_D3p
PS8338B_SW
PC11
IN_AUXp_A
OUT2_AUXp_SCL
IN_AUXn_A
OUT2_AUXn_SDA
PC10
PC21
PC20
OUT1_AUXn_SDA
OUT1_AUXp_SCL
PS8338B_PD
PS8338B_PD
PI1_A
OUT2_CA_DET_A
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