Clevo P150EM - Processor 2;7

Schematic Diagrams
TPM B - 3
B.Schematic Diagrams
TPM
TPM_BADD
Asserted before entering S3
LPC reset timing:
TPM 1.2
HI: 4E/ 4F H
LOW: 2E/ 2F H
HI: ACCESS
LOW: NORMAL ( Internal PD )
TPM_PP
LPCPD# inactive to LRST# inactive 32~96us
C792
*18p_50V_NPO_04
X15 *1TJS125DJ4A420P_32.768KHz
14
3 2
XTA LI
C791
*18p_50V_NPO_04
PCLK_TPM
R660 *10K_04
TPM_PP
R658 *10K_04
R659 *10K_04
R657 *33_04
LPC_AD220,35
LPC_AD120,35
PLT_RST#4,14,24
LPC_AD320,35
SUS_STAT#22
LPC_FRAME#20,35
PCLK_TPM24
PM_CLKRUN#22
SERIRQ20,35
LPC_AD020,35
C793 *10p_50V_04
3.3VS
C787
*0.1u_16V_Y 5V_04
C786
*0.1u_16V_Y5V_04
VDD3
C788
*0.1u_16V_Y 5V_04
3.3VS
C789
*1u_10V_06
C790
*0.1u_16V_Y5V_04
TPM_BAD D
TPM
U49
*SLB9635TT
LAD3
17
LAD0
26
LAD1
23
LAD2
20
VDD1
10
XTA L I
13
VDD3
24
VDD2
19
LFRAME#
22
LCLK
21
LRESET#
16
SERIRQ
27
CLKRUN#
15
GND_1
4
GND_2
11
GND_3
18
GND_4
25
GPIO
6
GPIO2
2
XTALO
14
TESTI
8
TESTBI/BADD
9
PP
7
NC_1
1
NC_2
3
NC_3
12
LPCPD#
28
VSB
5
TPM_PP
TPM Function ¤£¤W¥ó
TPM_BADD
XTA LO
D04
DEL X16
3.3VS4,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,33,34,35,36,37,38,41,45,48
VDD320,30,35,37,38,40,41,47
R570 *10K_04
3.3VS
bug 45
D03 modify
Sheet 2 of 61
TPM