CMOSTEK CMT2300A - CMT2300 A User Register Map

CMT2300A
Rev 1.0 | Page40/46
www.cmostek.com
8. User Register
CMT2300A is configured by writing in the registers. The following is the register table.
Table 21. CMT2300A Register Table
Addr R/W Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function
0x00 RW CUS_CMT1
0x01 RW CUS_CMT2
0x02 RW CUS_CMT3
0x03 RW CUS_CMT4
0x04 RW CUS_CMT5
0x05 RW CUS_CMT6
0x06 RW CUS_CMT7
0x07 RW CUS_CMT8
0x08 RW CUS_CMT9
0x09 RW CUS_CMT10
0x0A RW CUS_CMT11
0x0B RW CUS_RSSI
Addr R/W Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function
0x0C RW CUS_SYS1
0x0D RW CUS_SYS2 LFOSC_RECAL_EN LFOSC_CAL1_EN LFOSC_CAL2_EN RX_TIMER_EN SLEEP_TIMER_EN TX_DC_EN RX_DC_EN DC_PAUSE
0x0E RW CUS_SYS3 SLEEP_BYPASS_EN
0x0F RW CUS_SYS4
0x10 RW CUS_SYS5
0x11 RW CUS_SYS6
0x12 RW CUS_SYS7
0x13 RW CUS_SYS8
0x14 RW CUS_SYS9
0x15 RW CUS_SYS10 COL_DET_EN COL_OFS_SEL RX_AUTO_EXIT_DIS DOUT_MUTE
0x16 RW CUS_SYS11 PJD_TH_SEL
0x17 RW CUS_SYS12 CLKOUT_EN
Addr R/W Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function
0x18 RW CUS_RF1
0x19 RW CUS_RF2
0x1A RW CUS_RF3
0x1B RW CUS_RF4
0x1C RW CUS_RF5
0x1D RW CUS_RF6
0x1E RW CUS_RF7
0x1F RW CUS_RF8
Addr R/W Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function
0x20 RW CUS_RF9
0x21 RW CUS_RF10
0x22 RW CUS_RF11
0x23 RW CUS_RF12
0x24 RW CUS_FSK1
0x25 RW CUS_FSK2
0x26 RW CUS_FSK3
0x27 RW CUS_FSK4
0x28 RW CUS_FSK5
0x29 RW CUS_FSK6
0x2A RW CUS_FSK7
0x2B RW CUS_CDR1
0x2C RW CUS_CDR2
0x2D RW CUS_CDR3
0x2E RW CUS_CDR4
0x2F RW CUS_AGC1
0x30 RW CUS_AGC2
0x31 RW CUS_AGC3
0x32 RW CUS_AGC4
0x33 RW CUS_OOK1
0x34 RW CUS_OOK2
0x35 RW CUS_OOK3
0x36 RW CUS_OOK4
0x37 RW CUS_OOK5
Addr R/W Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function
0x38 RW CUS_PKT1 PREAM_LENG_UNIT
0x39 RW CUS_PKT2
0x3A RW CUS_PKT3
0x3B RW CUS_PKT4
0x3C RW CUS_PKT5 RESV SYNC_MAN_EN
0x3D RW CUS_PKT6
0x3E RW CUS_PKT7
0x3F RW CUS_PKT8
0x40 RW CUS_PKT9
0x41 RW CUS_PKT10
0x42 RW CUS_PKT11
0x43 RW CUS_PKT12
0x44 RW CUS_PKT13
0x45 RW CUS_PKT14 RESV AUTO_ACK_EN NODE_LENG_POS_SEL PAYLOAD_BIT_ORDER PKT_TYPE
0x46 RW CUS_PKT15
0x47 RW CUS_PKT16 RESV RESV NODE_FREE_EN NODE_ERR_MASK
0x48 RW CUS_PKT17
0x49 RW CUS_PKT18
0x4A RW CUS_PKT19
0x4B RW CUS_PKT20
0x4C RW CUS_PKT21 FEC_TYPE FEC_EN CRC_BYTE_SWAP CRC_BIT_INV CRC_RANGE CRC_EN
0x4D RW CUS_PKT22
0x4E RW CUS_PKT23
0x4F RW CUS_PKT24 CRC_BIT_ORDER WHITEN_SEED [8] WHITEN_SEED_TYPE WHITEN_EN MANCH_TYPE MANCH_EN
0x50 RW CUS_PKT25
0x51 RW CUS_PKT26 RESV RESV RESV RESV RESV RESV
0x52 RW CUS_PKT27
0x53 RW CUS_PKT28
0x54 RW CUS_PKT29 FIFO_AUTO_RES_EN
Addr R/W Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function
0x55 RW CUS_TX1
0x56 RW CUS_TX2
0x57 RW CUS_TX3
0x58 RW CUS_TX4
0x59 RW CUS_TX5
0x5A RW CUS_TX6
0x5B RW CUS_TX7
0x5C RW CUS_TX8
0x5D RW CUS_TX9
0x5E RW CUS_TX10
0x5F RW CUS_LBD
Addr R/W Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function
0x60 RW CUS_MODE_CTL
0x61 RW CUS_MODE_STA RESV RESV RSTN_IN_EN CFG_RETAIN
0x62 RW CUS_EN_CTL RESV RESV LOCKING_EN RESV RESV RESV RESV RESV
0x63 RW CUS_FREQ_CHNL
0x64 RW CUS_FREQ_OFS
0x65 RW CUS_IO_SEL RESV RESV
0x66 RW CUS_INT1_CTL RF_SWT1_EN RF_SWT2_EN INT_POLAR
0x67 RW CUS_INT2_CTL RESV LFOSC_OUT_EN TX_DIN_INV
0x68 RW CUS_INT_EN SL_TMO_EN RX_TMO_EN TX_DONE_EN PREAM_OK_EN SYNC_OK_EN NODE_OK_EN CRC_OK_EN PKT_DONE_EN
0x69 RW CUS_FIFO_CTL TX_DIN_EN FIFO_AUTO_CLR_DIS FIFO_TX_RD_EN FIFO_RX_TX_SEL FIFO_MERGE_EN SPI_FIFO_RD_WR_SEL
0x6A W CUS_INT_CLR1 RESV RESV SL_TMO_FLG RX_TMO_FLG TX_DONE_FLG TX_DONE_CLR SL_TMO_CLR RX_TMO_CLR
Addr R/W Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function
0x6B W CUS_INT_CLR2 RESV RESV LBD_CLR PREAM_OK_CLR SYNC_OK_CLR NODE_OK_CLR CRC_OK_CLR PKT_DONE_CLR
0x6C W CUS_FIFO_CLR RESV RESV RESV RESV RESV FIFO_RESTORE FIFO_CLR_RX FIFO_CLR_TX
0x6D R CUS_INT_FLAG LBD_FLG COL_ERR_FLG PKT_ERR_FLG PREAM_OK_FLG SYNC_OK_FLG NODE_OK_FLG CRC_OK_FLG PKT_OK_FLG
0x6E R CUS_FIFO_FLAG RESV RX_FIFO_FULL_FLG RX_FIFO_NMTY_FLG RX_FIFO_TH_FLG RX_FIFO_OVF_FLG TX_FIFO_FULL_FLG TX_FIFO_NMTY_FLG TX_FIFO_TH_FLG
0x6F R CUS_RSSI_CODE
0x70 R CUS_RSSI_DBM
0x71 R CUS_LBD_RESULT
User does not need to understand the details, just directly export the register contents from the RFPDK
CMT Bank
LMT_VTR [1:0]
MIXER_BIAS [1:0]
LNA_MODE [1:0]
LNA_BIAS [1:0]
System Bank
XTAL_STB_TIME [2:0]
TX_EXIT_STATE [1:0]
RX_EXIT_STATE [1:0]
SLEEP_TIMER_M [7:0]
SLEEP_TIMER_M [10:8]
SLEEP_TIMER_R [3:0]
RX_TIMER_T1_M [7:0]
RX_TIMER_T1_M [10:8]
RX_TIMER_T1_R [3:0]
RX_TIMER_T2_M [7:0]
User does not need to understand the details, just directly export the register contents from the RFPDK
Frequency Bank
RX_TIMER_T2_M [10:8]
RX_TIMER_T2_R [3:0]
RX_EXTEND_MODE [3:0]
CCA_INT_SEL [1:0]
RSSI_DET_SEL [1:0]
RSSI_AVG_MODE [2:0]
PJD_WIN_SEL [1:0]
CLKOUT_DIV [4:0]
RX_PREAM_SIZE [4:0]
User does not need to understand the details, just directly export the register contents from the RFPDK
Data Rate Bank
SYNC_VALUE [15:8]
SYNC_VALUE [23:16]
SYNC_VALUE [31:24]
SYNC_VALUE [39:32]
DATA_MODE [1:0]
Baseband Bank
TX_PREAM_SIZE [7:0]
TX_PREAM_SIZE [15:8]
PREAM_VALUE [7:0]
SYNC_TOL [2:0]
SYNC_SIZE [2:0]
SYNC_VALUE [7:0]
PAYLOAD_LENG [7:0]
NODE_SIZE [1:0]
NODE_DET_MODE [1:0]
NODE_VALUE [7:0]
NODE_VALUE [15:8]
SYNC_VALUE [47:40]
SYNC_VALUE [63:56]
PAYLOAD_LENG [10:8]
CRC_SEED [15:8]
WHITEN_TYPE [1:0]
WHITEN_SEED [7:0]
TX_PREFIX_TYPE [1:0]
NODE_VALUE [23:16]
NODE_VALUE [31:24]
CRC_TYPE [1:0]
CRC_SEED [7:0]
TX Bank
TX_PKT_NUM [7:0]
TX_PKT_GAP [7:0]
FIFO_TH [6:0]
User does not need to understand the details, just directly export the register contents from the RFPDK
TX_DIN_SEL [1:0]
Control Bank 2
RSSI_CODE [7:0]
RSSI_DBM [7:0]
LBD_RESULT [7:0]
CHIP_MODE_SWT [7:0]
Control Bank 1
CHIP_MODE_STA [3:0]
FH_CHANNEL [7:0]
FH_OFFSET [7:0]
GPIO3_SEL [1:0]
GPIO2_SEL [1:0]
GPIO1_SEL [1:0]
INT1_SEL [4:0]
INT2_SEL [4:0]