Cmsemicon SC8F577 Series - Page 64

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7.2.3 Peripherals Interrupt Request Register
The peripherals interrupt request register is PIR1 and PIR2. When an interrupt condition occurs,
regardless of the state of the corresponding interrupt enable bit or the global enable bit GIE, the interrupt flag
bit will be set to 1. The user software should ensure that the interrupt is set before allowing an interrupt. The
corresponding interrupt flag bit is cleared.
Peripherals interrupt request register PIR1 (0CH)
0CH
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIR1
----
EEIF
RCIF
TXIF
SPIIF
PWMIF
TMR2IF
ADIF
R/W
----
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
----
0
0
0
0
0
0
0
Bit7
Not used.
Bit6
EEIF:
Program EEPROM write operation interrupt bit；
1=
program EEPROM write operation complete (must clear through software)；
0=
program EEPROM write operation not complete or not start.
Bit5
RCIF:
USART receive interrupt flag bit；
1=
USART receive buffer full (clear through reading RCREG)；
0=
USART receive buffer empty.
Bit4
TXIF:
USART transmit interrupt flag bit；
1=
USART transmit buffer full (clear through TXREG)；
0=
USART transmit buffer empty.
Bit3
SPIIF:
SPI interrupt flag bit.
1=
SPI receive /transmit interrupt happens (must clear through software);
0=
No SPI interrupt condition is met.
Bit2
PWMIF:
PWM interrupt flag bit.
1=
PWM interrupt happens (must clear through software);
0=
PWM interrupt not happen
Bit1
TMR2IF:
TIMER2 and PR2 match interrupt flag bit.
1=
TIMER2 and PR2 match happens (must clear through software)；
0=
TIMER2 and PR2 not match.
Bit0
ADIF:
A/D converter interrupt flag bit；
1=
A/D conversion complete (must clear through software)；
0=
A/D conversion not complete or not start.